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AR7242 Schematic ( PDF Datasheet ) - Atheros

Teilenummer AR7242
Beschreibung A High Performance And Cost-Effective Network Processor
Hersteller Atheros
Logo Atheros Logo 




Gesamt 30 Seiten
AR7242 Datasheet, Funktion
Data Sheet
April 2011
AR7242: A High Performance And Cost-Effective Network
Processor
General Description
The Atheros AR7242 is a high performance
and cost effective network processor for access
point, router, and gateway applications. It
includes a MIPS 24Kc processor, PCI Express
1.1 host interface, integrated 10/100 Mbps
Fast Ethernet MAC/PHY, one RGMII port,
one USB 2.0 MAC/PHY, and external memory
interface for serial Flash, DDR1 or DDR2
interface, an I2S audio interface, a high-speed
UART, and GPIOs that can be used for LED
controls or other general purpose interface
configurations.
The AR7242 is a memory-centric architecture
including various DMA controlled interfaces
that access the DDR memory.
The AR7242 network processor, when paired
with the AR928x/AR938x/AR939x single
chip 802.11n MAC/BB/Radio family,
provides the best-in-class WLAN solution
capable of supporting 802.11b/g/n standards.
Features
Integrated MIPS 24 K 32-bit processor
operating at up to 400 MHz
64 K instruction cache and 32 K data cache
Integrated 10/100 802.3 Ethernet LAN port
and one RGMII port
16-bit DDR1 or DDR2 memory interface
supporting up to 400 M transfers per
second
An external serial Flash memory interface
(maximum 16 MBytes)
One USB 2.0 controller with built-in MAC/
PHY
High-speed UART and multiple GPIO pins
for general purpose I/O or LED control
A single lane PCI Express 1.1 interface that
can be used for interfacing to the AR928x/
AR938x/AR939x single chip 802.11n
MAC/BB/Radio
JTAG port support for processor core
14 mm x 14 mm 128-pin LQFP lead-free
package
System Block Diagram
© 2010-2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, ETHOS®, IQUE®, No
New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, ROCm™,
amp™, Install N Go™, Simpli-Fi™, SmartLink™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered
trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1






AR7242 Datasheet, Funktion
PRELIMINARY
4.9.13 PCIE Spare Bits (PCIE_SPARE) 85
4.9.14 PCIE MSI Lower Address
(PCIE_MSI_ADDR) .................... 85
4.9.15 PCIE MSI Data Value
(PCIE_MSI_DATA) .................... 85
4.9.16 PCIE Interrupt Status
(PCIE_INT_STATUS) ................. 86
4.9.17 PCIE Interrupt Mask
(PCIE_INT_MASK) .................... 87
4.10 Ethernet Registers ................................. 88
4.10.1 MAC Configuration 1 ................ 91
4.10.2 MAC Configuration 2 ................ 92
4.10.3 IPG/IFG ....................................... 93
4.10.4 Half-Duplex ................................. 94
4.10.5 Maximum Frame Length ........... 94
4.10.6 MII Configuration ....................... 95
4.10.7 MII Command ............................. 95
4.10.8 MII Address ................................. 96
4.10.9 MII Control .................................. 96
4.10.10 MII Status ................................... 96
4.10.11 MII Indicators ............................ 96
4.10.12 Interface Control ....................... 97
4.10.13 Interface Status .......................... 98
4.10.14 STA Address 1 ........................... 99
4.10.15 STA Address 2 ........................... 99
4.10.16 ETH_FIFO RAM Configuration 0
100
4.10.17 ETH Configuration 1 .............. 101
4.10.18 ETH Configuration 2 .............. 101
4.10.19 ETH Configuration 3 .............. 102
4.10.20 ETH Configuration 4 .............. 103
4.10.21 ETH Configuration 5 .............. 103
4.10.22 Tx/Rx 64 Byte Frame Counter
(TR64) ......................................... 104
4.10.23 Tx/Rx 65-127 Byte Frame Counter
(TR127) ....................................... 104
4.10.24 Tx/Rx 128-255 Byte Frame
Counter (TR255) ........................ 104
4.10.25 Tx/Rx 256-511 Byte Frame
Counter (TR511) ........................ 104
4.10.26 Tx/Rx 512-1023 Byte Frame
Counter (TR1K) ......................... 105
4.10.27 Tx/Rx 1024-1518 Byte Frame
Counter (TRMAX) .................... 105
4.10.28 Tx/Rx 1519-1522 Byte VLAN
Frame Counter (TRMGV) ........ 105
6 • AR7242 Network Processor
6 April 2011
4.10.29 Receive Byte Counter (RYBT) 105
4.10.30 Receive Packet Counter (RPKT) .
106
4.10.31 Receive FCS Error Counter (RFCS)
106
4.10.32 Receive Multicast Packet Counter
(RMCA) ...................................... 106
4.10.33 Receive Broadcast Packet Counter
(RBCA) ....................................... 106
4.10.34 Receive Control Frame Packet
Counter (RXCF) ........................ 107
4.10.35 Receive Pause Frame Packet
Counter (RXPF) ......................... 107
4.10.36 Receive Unknown OPCode Packet
Counter (RXUO) ....................... 107
4.10.37 Receive Alignment Error Counter
(RALN) ....................................... 107
4.10.38 Receive Frame Length Error
Counter (RFLR) ......................... 108
4.10.39 Receive Code Error Counter
(RCDE) ....................................... 108
4.10.40 Receive Carrier Sense Error
Counter (RCSE) ......................... 108
4.10.41 Receive Undersize Packet Counter
(RUND) ...................................... 108
4.10.42 Receive Oversize Packet Counter
(ROVR) ....................................... 109
4.10.43 Receive Fragments Counter
(RFRG) ........................................ 109
4.10.44 Receive Jabber Counter (RJBR) 109
4.10.45 Receive Dropped Packet Counter
(RDRP) ....................................... 109
4.10.46 Transmit Byte Counter (TBYT) 110
4.10.47 Transmit Packet Counter (TPKT)
110
4.10.48 Transmit Multicast Packet Counter
(TMCA) ...................................... 110
4.10.49 Transmit Broadcast Packet
Counter (TBCA) ........................ 110
4.10.50 Transmit Pause Control Frame
Counter (TXPF) ......................... 111
4.10.51 Transmit Deferral Packet Counter
(TDFR) ........................................ 111
4.10.52 Transmit Excessive Deferral Packet
Counter (TEDF) ........................ 111
4.10.53 Transmit Single Collision Packet
Counter (TSCL) ......................... 111
4.10.54 Transmit Multiple Collision Packet
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

6 Page









AR7242 pdf, datenblatt
PRELIMINARY
Table 1-2. Signal-to-Pin Relationships and Descriptions
Symbol
Reset and Clock
REFCLKIN
RST_L
SYS_RST_OUT_L
PCI Express
PCIE_CLKOUT_N
PCIE_CLKOUT_P
PCIE_RST_OUT_L
PCIE_RX_N
PCIE_RX_P
PCIE_TX_N
PCIE_TX_P
Serial Interface
SPI_CLK[1]
SPI_CS_EN0[1]
SPI_CS_EN1[1]
SPI_CS_EN2[1]
SPI_MOSI[1]
SPI_MISO[1]
USB
USB_DM
USB_DP
USB_REXT
UART
UART_CTS[1]
UART_RTS[1]
UART_SIN[1]
UART_SOUT[1]
Pin Type Description
94 I 40 MHz reference clock input, AC coupled, can be sine wave or
square wave. An external 100 pF capacitor should connect
between REFCLKIN and the clock source. See Table 5-8 and
Table 5-9 on page 184 for more information.
93 IH Power on reset with internal weak pull-up. Refer to reference
design schematics
111 OD System reset out, open drain, pull up is required
104 OA Differential reference clock (100 MHz)
103 OA
102 OD PCI Express reset, open drain
101 IA Differential receive
100 IA
99 OA Differential transmit
98 OA
76 O Serial interface clock
80 O SPI chip select
107 O
108 O
77 O Data transmission from the AR7242 to an external device. On
reset, SPI_MISO (GPIO_5) is input and SPI_MOSI (GPIO_4) is
output so it can directly interface with a SPI device such as a serial
flash. If a serial flash is not used, these pins may be used as GPIO
pins.
78 IL Data transmission from an external device to the AR7242. On
reset, SPI_MISO (GPIO_5) is input and SPI_MOSI (GPIO_4) is
output so that it can directly interface with a SPI device such as a
serial flash. If a serial flash is not used, these pins may be used as
GPIO pins.
73 A USB 2.0
74 A USB 2.0
75 A USB 2.0
89 I UART clear to send signal
88 O UART ready to send signal (optional UART interface pin)
86 I Serial data in
87 O Serial data out
12 • AR7242 Network Processor
12 April 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

12 Page





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