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AR7100 Schematic ( PDF Datasheet ) - Atheros

Teilenummer AR7100
Beschreibung High Performance And Cost-Effective Network Processor
Hersteller Atheros
Logo Atheros Logo 




Gesamt 30 Seiten
AR7100 Datasheet, Funktion
Data Sheet
December 2008
AR7100: A Scalable, High Performance And Cost-Effective
Network Processor Family
General Description
Features
The Atheros AR7100 is a scalable, high
performance and cost effective network
processor family that allows efficient design of
solutions addressing triple play services such
as voice, video and data for home and
enterprise access point, router and gateway
applications. It includes a 32-bit MIPS
processor, PCI host interface, two 802.3
Ethernet MACs with GMII/RGMII/RMII/MII
interface, two USB 2.0 MAC/PHYs, a PCM
interface for glueless SLIC support, external
memory interface for serial Flash and DDR-
SDRAM, a high-speed UART, I2S interface, and
GPIOs that can be used for LED controls.
The AR7100 network processor when paired
with the AR9100 chipset family (AR9160
MAC/baseband processor and AR9106/
AR9104/AR9103/AR9102/AR9101 radios)
provides the best in class WLAN solution
capable of supporting 802.11a/b/g/n
standards.
Integrated MIPS 24K-family processor
300–680 MHz processor frequency:
– AR7130, 300 MHz, Fast Ethernet version
– AR7141, 400 MHz, supports Fast
Ethernet and GB Ethernet
– AR7161, 680 MHz, supports Fast
Ethernet and GB Ethernet
High Performance DDR memory controller
(16- or 32-bit)
Dual IEEE 802.3 Ethernet MAC supporting
10/100/1000 Mbps, full and half duplex
and GMII/RGMII/RMII/MII interfaces
Two-port USB 2.0 Host Controllers with
built-in MAC/PHY
UART for console support
32-bit, 33/66 MHz PCI 2.3 host interface
supporting up to three client devices
IEEE 1149.1 standard test access port and
boundary scan architecture supported
JTAG based debugging of the processor
core supported
13 mm x 13 mm 384 TFBGA lead-free
package
Along with the Atheros AR9100 (MAC/BB
and radio chips) family—Completes an all-
CMOS solution for 802.11a/b/g/n WLANs,
supporting extended range for worldwide
operations
System Block Diagram
2.4/5 GHz
3x
FEM
DDR Controller
and Memory
Interface
AR9103/
AR9106
AR9160
AR9100
40
MHz
Crystal
PCI
Interface
MIPS Processor
AR7100
Ethernet MAC
Ethernet MAC
High Speed UART
USB MAC/PHY
USB MAC/PHY
External Interface
PCM Interface
I2S
Serial Flash/DDR Interface
RGMII Interface
RGMII Interface
UART Interface
USB 2.0 Interface
USB 2.0 Interface
GPIOs/LEDs
SLIC
Audio Interface
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super
AG®, Super G®, Total 802.11n®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air
is Cleaner at 5-GHz™, XSPAN™, Wireless Future. Unleashed Now.™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1






AR7100 Datasheet, Funktion
5.13.8 MII Address ................................. 94
5.13.9 MII Control .................................. 94
5.13.10 MII Status ................................... 94
5.13.11 MII Indicators ............................ 94
5.13.12 STA Address 1 ........................... 95
5.13.13 STA Address 2 ........................... 95
5.13.14 Transmit FIFO Threshold ........ 95
5.13.15 Rx Filter Match .......................... 96
5.13.16 Rx Filter Mask ............................ 96
5.14 DMA Registers ...................................... 97
5.14.1 Transmit Control
(DMA_TX_CTRL) ....................... 97
5.14.2 Pointer-to-Tx Descriptor
(DMA_TX_DESCRIPTOR) ........ 97
5.14.3 Tx Status (DMA_TX_STATUS) . 98
5.14.4 Rx Control (DMA_RX_CTRL) .. 98
5.14.5 Pointer-to-Rx Descriptor
(DMA_RX_DESCRIPTOR) ........ 98
5.14.6 Receive Status
(DMA_RX_STATUS) .................. 99
5.14.7 Interrupt Mask
(DMA_INTR_MASK) ................. 99
5.14.8 Interrupts (DMA_INTERRUPT) ...
100
5.15 DMA Descriptor Definitions ............. 100
5.15.1 Packet Data Start Address
(PACKET_START_ADDR) ..... 101
5.15.2 Size of Packet, Overrides, and
Empty Flag (PACKET_SIZE) .. 101
5.15.3 Next Descriptor Location
(NEXT_DESCRIPTOR) ............ 101
5.16 SPI Registers ........................................ 102
5.16.1 Function Select .......................... 102
5.16.2 SPI Control ................................. 102
5.16.3 SPI I/O Control ......................... 103
5.16.4 SPI Read Data Shift ................... 103
6 Package Dimensions ................. 105
7 Ordering Information ............... 107
Index ................................................. 109
6 • AR7100 Network Processor Family
6 December 2008
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

6 Page









AR7100 pdf, datenblatt
Table 1-5. Signal-to-Pin Relationships (continued)
Signal Name
UART
UART_SIN[1]
UART_SOUT[1]
SPI Interface
SPI_CLK
SI_CS1_L[1]
SI_CS2_L[1]
SPI_CS_L
SPI_MI_SO
SPI_MO_SI
DDR
DDR_A_0
DDR_A_1
DDR_A_2
DDR_A_3
DDR_A_4
DDR_A_5
DDR_A_6
DDR_A_7
DDR_A_8
DDR_A_9
DDR_A_10
DDR_A_11
DDR_A_12
DDR_BA_0
DDR_BA_1
DDR_CAS_L
DDR_RAS_L
DDR_CK_N
DDR_CK_P
DDR_CKE_L
DDR_CS_L
Pin
C19
A18
B14
C20
B21
A15
B15
A14
Y2
AA2
AB2
AC3
AD2
AC1
AB1
AA1
Y1
W1
W2
V1
U1
V2
W3
AA3
AB3
R1
T1
U3
AB4
Pull-Up/
Direction Pull-Down Voltage Description
I
None
3.3 V Serial data in
O
None
3.3 V Serial data out
O
None
3.3 V Serial interface clock
O
None
3.3 V Optional serial interface chip select, for
controlling external serial devices
O
None
3.3 V Optional serial interface chip select, for
controlling external serial devices
O
None
3.3 V SPI chip select
I
None
3.3 V Data transmitted from an external device to the
AR7100
O
None
3.3 V Data transmitted from the AR7100 to an external
device
O
None
2.5 V DDR address
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V
O
None
2.5 V DDR bank address
O
None
2.5 V
O
None
2.5 V DDR column address strobe
O
None
2.5 V DDR row address strobe
O
None
2.5 V DDR clock
O
None
2.5 V
O
None
2.5 V DDR clock enable
O
None
2.5 V DDR chip select
12 • AR7100 Network Processor Family
12 December 2008
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

12 Page





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