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OXE800DSE Schematic ( PDF Datasheet ) - Oxford Semiconductor

Teilenummer OXE800DSE
Beschreibung Network Attached Storage Device
Hersteller Oxford Semiconductor
Logo Oxford Semiconductor Logo 




Gesamt 16 Seiten
OXE800DSE Datasheet, Funktion
Features
Data Sheet
OXE800DSE
Network Attached Storage Device
„ Flexible, extendable storage
† Seamless interface to 2 internal SATA drives, expandable
via PCI SATA bridge chips
„ Accessible from multiple clients using Ethernet (integrated 10/
100 Ethernet MAC) or 802.11 WiFi (via PCI WiFi chips)
„ 200-MHz ARM926EJ-S processor with 32-Kbyte caches & MMU
„ Network coprocessor
† TCP / IP acceleration
„ Supports multiple software architectures
† Linux OS
† TCP/IP & CIFS
† EXT3
„ Simple to install—no specialist user knowledge necessary;
automatic installation with DHCP client & simple configuration
„ RAID 1 hardware accelerator
„ Integrated fan/tacho/PWM
„ AES-based encryption supports multiple authentication methods
& devices for secure storage of user data
„ 5-channel DMA controller
„ USB 2.0 & USB full-speed host controllers
„ 32-Kbyte on-chip SRAM
„ DDR SDRAM controller with selectable 8 & 16-bit interface
supports combinations up to 64 Mbytes addressable storage
„ 16-bit static memory interface (optional—device boots from
HDD) supports up to 4 Mbytes addressable storage per chip-
select
„ 0.13-μm CMOS process with 1.2-V core
„ 19 mm×19 mm 272-pin PBGA (1-mm ball pitch)
DS-0025 Oct 07
External—Free Release
1






OXE800DSE Datasheet, Funktion
OXE800DSE Network Attached Storage Device
Oxford Semiconductor, Inc.
Electrical
Characteristics
Table 3 details the required DC electrical characteristics for the device.
Table 3 3.3-V I/O Buffer Electrical Characteristics
Symbol
VIH
VIL
VT
Parameter
Input high voltage
Input low voltage
Switching threshold
Condition
CMOS Interface
CMOS Interface
Min
2.0
VT + Schmitt trigger, positive-going threshold CMOS
VT - Schmitt trigger, negative-going
threshold
CMOS
0.8
IIH Input high current:
Input buffer
Input buffer with pull-down
VIN = VDD
–10
10
IIL Input low current:
Input buffer
Input buffer with pull-up
VOH Output high voltage
VOL Output low voltage
IOZ Tri-state output leakage current
IDD Quiescent supply current
CIN Input capacitance
VIN = VSS
IOH = –1 μA
IOH = –1 mA to –24 mA
IOL = 1 μA
IOL = 1 mA to 24 mA
VOUT = VSS or VDD
–10
–60
VDD – 0.05
2.4
-10
Any input & bidirectional
buffers
COUT
Output capacitance
Any output buffer
Type
1.4
33
–33
Max Units
V
0.8 V
V
2.0 V
V
μA
10
60
μA
10
–10
V
0.05 V
0.4
10 μA
100 μA
4 pF
4 pF
6
External—Free Release
DS-0025 Oct 07

6 Page









OXE800DSE pdf, datenblatt
OXE800DSE Network Attached Storage Device
Oxford Semiconductor, Inc.
Table 5 OXE800DSE Pin Allocations (Sheet 4 of 4)
Ball
G16
H16
J16
L11,L12,H11,H12
K12,K11,J11,J12
F15
F14
F16,F17,H15,J15,J17,J18,K15,
M18
M2
K1
K4,J7
K7,K2
M1,L3,K9
R3,U3
A1,R16,T15,T16,D5,J8,M7,M10,
K10,H7,L8,L9,M11,J10,V4
E4,L7,M8,M12,H8
D4,J9,P6,M9,L10,T11,T12,T13,
T14
E13,G12,D11,H10,H9,G8,E6,F5
E14,C12,D7,D13,G11,D9,G10,
G9,G7,D6,E5
E15,D12,D8
N16,T9
R15,T10
NC (9 pins)
N5,P4,R3,T1,T5,U3,T4,R6,U1
No.
Bits
1
1
1
4
4
1
1
8
1
1
2
2
3
2
15
5
9
8
11
3
2
2
9
Type(1)
Name
P SATA0_VDDTX0
P SATA1_VDDRX0
P SATA0_VDDRX1
P SATA_VSSPLL
P SATA_VDDPLL
P SATA_VSSOSC
P SATA_VDDOSC
P SATA_VSS
P USB_VDDA33C
P USB_VSSA33C
P USB_VDD12
P USB_VSS12
P USB_VSSA33T1
P USB_VDDA33T1
P VSS
P VDD12
P VDD33
P VDD25_MEM
P VSS_MEM
P VDD12_MEM
P VDD12_PCI
P VSS_PCI
Description
SATA Tx power (1.2 V)
SATA Rx power (1.2 V)
SATA Rx power (1.2 V)
SATA PLL ground
PLL supply (1.2 V)
SATA ground for the crystal oscillator
SATA 3.3-V power supply for the crystal oscillator
Ground
Analog 3.3-V supply
Analog ground
Digital 1.2-V supply
Digital ground
Analog ground
Analog 3.3-V supply
Ground
1.2-V supply
3.3-V supply
2.5-V SDRAM interface supply
SDRAM interface ground
1.2-V SDRAM interface supply
1.2-V PCI bus interface supply
PCI ground
Do not connect
Notes:
1 Type key: format is [(W_)X)] where the following conventions apply:
W—Supply
5V 5-V tolerant 3.3 V
3V3 3.3 V
2V5 2.5
X—Type
I Input
O Output
B Bidirectional
A Analog
2 Any of the 35 GPIO pins on the device can be assigned to a primary function, a secondary func-
tion or bit-programmable general-purpose I/O in response to peripheral control register ter-
tiary settings.JTAG must not be enabled in conjunction with HIGH_Z_N asserted low.
12
External—Free Release
DS-0025 Oct 07

12 Page





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