9.2.17 Data Identifier (DI)...................................................................................................................................117
9.2.18 Victual Channel Identifier (VC) ................................................................................................................118
9.2.19 Data Type (DT) .........................................................................................................................................118
9.3 OPERATING MODES ...........................................................................................................................................122
9.3.2 State machine operation............................................................................................................................135
9.3.3 D-PHY operation ......................................................................................................................................136
9.3.4 Analog Transceiver ...................................................................................................................................137
9.3.5 PLL ...........................................................................................................................................................137
9.3.6 Clock Source Example ..............................................................................................................................138
10 EXTERNAL INTERFACE.................................................................................................. 139
10.1 SPI INTERFACE 8 BIT 4 WIRE.............................................................................................................................139
10.2 SPI INTERFACE 8 BIT 3 WIRE.............................................................................................................................141
10.2.1 3 or 4 wires 8bit SPI read back sequence for 0xFF register which is stored MIPI read back data .........143
10.3 SPI INTERFACE 24 BIT 3 WIRE...........................................................................................................................145
10.3.1 3 wires 24bit SPI read back sequence for 0xFF register which is stored MIPI read back data...............147
11 MAXIMUM RATINGS........................................................................................................ 149
12 RECOMMENDED OPERATING CONDITIONS ........................................................... 150
13 DC CHARACTERISTICS................................................................................................... 151
14 AC CHARACTERISTICS................................................................................................... 153
14.1 8 BIT 4 WIRE SPI INTERFACE TIMING................................................................................................................154
14.2 8 BIT 3 WIRE SPI INTERFACE TIMING................................................................................................................155
14.3 24 BIT 3 WIRE SPI INTERFACE TIMING..............................................................................................................156
14.4 RGB INTERFACE TIMING...................................................................................................................................157
14.5 RESET TIMING .................................................................................................................................................158
14.6 TX_CLK TIMING ..............................................................................................................................................158
15 POWER UP SEQUENCE .................................................................................................... 159
16 POWER OFF SEQUENCE ................................................................................................. 160
17 EXAMPLE FOR SYSTEM SLEEP IN AND OUT ........................................................... 161
18 SERIAL LINK DATA ORDER........................................................................................... 162
19 PACKAGE INFORMATION.............................................................................................. 165
19.1 DIMENSION FOR SSD2828QN4 .........................................................................................................................165
SSD2828QN4
Rev 1.3 P 5/168 Mar 2013
Solomon Systech
3 ORDERING INFORMATION
Table 3-1: Ordering Information
Ordering Part Number
SSD2828QN4
Package Form
68 QFN-EP (in Tray form)
4 BLOCK DIAGRAM
The SSD2828 IC consists of the following modules.
• Clock and reset module
• External interface
• PCU (protocol control unit)
• PPU (packet processing unit)
• ECC/CRC
• Long and command buffers
• D-PHY controller
• Analog MIPI transceiver
• Internal PLL
The usage of SSD2828 is given in the diagram below.
Application
processor
SSD2828
Parallel LCD
interface or
Serial SPI
interface
LCD driver with
MIPI slave
interface
Figure 4-1: Overview of display system using SSD2828
SSD2828QN4
Rev 1.3 P 11/168 Mar 2013
Solomon Systech