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PDF BK2412 Data sheet ( Hoja de datos )
| Número de pieza | BK2412 | |
| Descripción | 2.4-GHz FSK/GFSK Transceiver IC | |
| Fabricantes | Beken | |
| Logotipo |  |
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BK2411/BK2412
v0.5
BK2411/BK2412
Preliminary Specifications
2.4-GHz FSK/GFSK Transceiver IC
Beken Corporation
Suite 303-304, No. 10, 198 Zhangheng Rd, Shanghai 201204, China
PHONE: (86)21 6160 9676/7/8
FAX: (86)21 6160 9679
This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The contents of this
document should not be disclosed outside the companies without specific written permission.
Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware implementation may differ.
© 2008 Beken Corporation
Proprietary and Confidential
Page 1 of 31
1 page  
BK2411/BK2412
v0.5
Figure 3 BK2411 pin assignment (top view) for the QFN20 4x4 package
Table 1 BK2411 chip pin functions
PIN Name Pin Function
1 CE
Digital Input
2 CSN Digital Input
3 SCK Digital Input
4
MOSI
Digital Input
5
MISO
Digital Output
6 IRQ
Digital Output
7 VDD Power
8 VSS Ground
9
XTALP
Analog Input
10
XTALN
Analog Output
11 VDDPA Power
12 RFP
RF port
13 RFN
RF port
14 VSS
Ground
15 VDD
Power
16 IREF
Analog Output
17 VSS
Ground
18 VDD
Power
19 CDVDD Analog Output
20 VSS
Ground
Description
Chip Enable Activates RX or TX mode
SPI Chip Select
SPI Clock
SPI Slave Data Input
SPI Slave Data Output with tri-state option
Mask able interrupt pin. Active low
Power Supply (1.9 V to 3.3 V DC)
Ground (0 V)
Crystal oscillator, node P (inverter output)
Crystal oscillator, node N (inverter input)
1.8V Regulated output for PA
RF output (PA) /input (LNA), port P.
RF output (PA) /Input (LNA), port N.
Ground (0 V)
Power Supply (1.9 V to 3.3 V DC)
Analog output; reference current generation
Ground (0 V)
Power Supply (1.9 V to 3.3 V DC)
Digital regulator output decoupling cap
Ground (0 V)
© 2008 Beken Corporation
Proprietary and Confidential
Page 5 of 31
5 Page 
BK2411/BK2412
Figure 7 Packet Format at Normal Payload Mode
v0.5
Figure 8 Packet Format at Long Payload Mode
In normal payload mode, there are three levels 32 bytes FIFO for both TX and RX,
supporting both acknowledge mode or no acknowledge mode with up to six pipes.
In long payload mode, there is single level 255 bytes TX and RX FIFO.
Payload mode can be selected by LONG_PL register in register bank 1.
6.4.1.1 Preamble
The preamble is a bit sequence used to detect 0 and 1 levels in the receiver. The preamble
is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the
preamble is automatically set to 10101010 and if the first bit is 0 the preamble is
automatically set to 01010101. This is done to ensure there are enough transitions in the
preamble to stabilize the receiver.
6.4.1.2 Address
This is the address for the receiver. An address ensures that the packet is detected by the
target receiver. The address field can be configured to be 3, 4, or 5 bytes long by the AW
register.
The PRX device can open up to six data pipes to support up to six PTX devices with
unique addresses. All six PTX device addresses are searched simultaneously. In PRX side,
the data pipes are enabled with the bits in the EN_RXADDR register. By default only
data pipe 0 and 1 are enabled.
Each data pipe address is configured in the RX_ADDR_PX registers.
Each pipe can have up to 5 bytes configurable address. Data pipe 0 has a unique 5 byte
address. Data pipes 1-5 share the 4 most significant address bytes. The LSB byte must be
© 2008 Beken Corporation
Proprietary and Confidential
Page 11 of 31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BK2412.PDF ] | |
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