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PDF MT6260A Data sheet ( Hoja de datos )
| Número de pieza | MT6260A | |
| Descripción | GSM/GPRS/EDGE-RX SOC | |
| Fabricantes | MEDIATEK | |
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MT6260A GSM/GPRS/EDGE-RX SOC
Processor Technical Brief
Version:
1.1
Release date: 2013-03-19
© 2013 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
Specifications are subject to change without notice.
1 page  
MT6260A
GSM/GPRS/EDGE-RX SOC Processor Technical Brief
v1.1 Confidential A
Figure 13. PCHR block diagram. .......................................................................................................... 73
Figure 14. Charging states diagram...................................................................................................... 74
Figure 15. Diagram of MT6260A 2G RFSYS ........................................................................................ 79
Figure 16. System diagram of Bluetooth RF transceiver ...................................................................... 84
Figure 17. Block diagram of hardware top-level architecture ............................................................... 88
Figure 18. Outlines and dimension of TFBGA 9.6mm*8.6mm, 199-ball, 0.5 mm pitch package ......... 93
Figure 19 Mass production top marking of MT6260A .......................................................................... 94
MediaTek Confidential
© 2013 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this informa ion in whole or in part is strictly prohibited.
Page 5 of 94
5 Page 
MT6260A
GSM/GPRS/EDGE-RX SOC Processor Technical Brief
v1.1 Confidential A
1.1 Platform Features
General
Integrated voi e-band, audio-band and
base-band analog front-end
Integrated f ll-fe tured power management
unit
MCU subsystem
ARM7EJ-STM 32-bit RISC processor
Java hardware acceleration for fast
Java-based games and applets
High-performance multi-layer AHB bus
Dedicated DMA bus with 15 DMA channels
On-chip boot ROM for factory fla h
programming
Watchdog timer for system crash recov ry
4 sets of general-purpose timers
Circuit switch data coprocessor
Division coprocessor
Serial flash interfaces
Supports various operating frequency
combinations for serial flash
Supports QPI and SPI serial flash
User interfaces
5-row x 5-column keypad controller with
hardware scanner
Supports multiple key presses for gaming
Dual SIM/USIM controller with hardware T =
0/T = 1 protocol control
Real-time clock (RTC) operating with a
low-quiescent-current power supply
General-purpose I/Os (GPIOs) available for
auxiliary applications
1 sets of Pulse Width Modulation (PWM)
output
16 external interrupt lines
1 external channel auxiliary 10-bit A/D
converter
Security
Supports security key and chip random ID
Connectivity
2 UARTs with hardware flow control and
supports baud rate up to 921,600 bps
FS/LS USB 1.1 device controller
Multimedia card, secure digital Memory Card,
host controller with flexible I/O voltage power
Supports SDIO interface for SDIO
peripherals as well as WIFI connectivity
DAI/PCM and I2S interface for audio
applications
I2C master interface for peripheral
management including image sensors
SPI master interface for peripheral
mana ement.
Power management
Li-ion battery charger
14 LDOs fo the power supply of memory
card, camera, Bluetooth, RF, SIM card and
other diversified usage
4 open-drain outpu switches to
supply/control the LED
LDO type vibrato
One NMOS switch to control keypad LED
Thermal overload protection
Under-voltage lock-out prot ction
Over-voltage protection
Different levels of sleep modes with
sophisticated software control enables
excellent power saving performance.
MediaTek Confidential
© 2013 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this informa ion in whole or in part is strictly prohibited.
Page 11 of 94
11 Page | ||
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