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HD66760 Schematic ( PDF Datasheet ) - Hitachi Semiconductor

Teilenummer HD66760
Beschreibung 104 x 80-dot Graphics LCD Controller/Driver
Hersteller Hitachi Semiconductor
Logo Hitachi Semiconductor Logo 




Gesamt 30 Seiten
HD66760 Datasheet, Funktion
HD66760
104 × 80-dot Graphics LCD Controller/Driver for 256 Colors
ADE-207-335A(Z)
Rev.2.0
September 2001
Description
The HD66760, color-graphics LCD controller and driver LSI, displays 104-by-80-dot graphics for 256 STN
colors. The HD66760's bit-operation functions and a 16-bit high-speed bus interface enable efficient data
transfer and high-speed rewriting of data to the graphics RAM.
The HD66760 has various functions for reducing the power consumption of an LCD system, such as low-
voltage operation of 2.2 V/min., a step-up circuit to generate a maximum of six-times the LCD drive voltage
from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-
resistors. Combining these hardware functions with software functions, such as a partial display with low-
duty drive and standby and sleep modes, allows precise power control. The HD66760 is suitable for any mid-
sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular
phones supporting a WWW browser, bidirectional pagers, and small PDAs.
Features
104 × 80-dot graphics display LCD controller/driver for 256 STN colors
Display mode change between 256 colors (8 bits per pixel) and four colors (2-bit per pixel)
16/8-bit high-speed bus interface
I2C bus interface
Clock synchronized serial interface
Bit-operation functions for graphics processing:
Write-data mask function in bit units
Swap function of upper and lower bytes
Logical operation in pixel unit and conditional write function
Various color-display control functions:
256 of the 4,096 possible colors can be displayed at the same time (grayscale palette incorporated)
Vertical scroll display function in raster-row units
Color window cursor display supported by hardware
Low-power operation supports:
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.






HD66760 Datasheet, Funktion
HD66760
HD66760 Pad Coordinates
(Unit : um)
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HD66760 pdf, datenblatt
HD66760
Address Counter (AC)
The address counter (AC) assigns addresses to the GRAM. When an address set instruction is written into the
IR, the address information is sent from the IR to the AC.
After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading
from the data, the AC is not updated.
Graphics RAM (GRAM)
The graphics RAM (GRAM) has eight bits/pixel and stores the bit-pattern data of 104 × 80 bytes.
Grayscale Palette (GSP)
The grayscale palette (GSP) is a palette table that converts the information (three bits for each color: two bits
for B) read from the GRAM to 4-bit grayscale data. Any 256 of the 4,096 possible colors can be displayed at
the same time. For details, see the Grayscale Palette section.
Grayscale Control Circuit
The grayscale control circuit performs 16-grayscale control with the frame rate control (FRC) method for
grayscale display for each color. For details, see the Grayscale Palette section.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The
RAM read timing for display and internal operation timing by MPU access are generated separately to avoid
interference with one another.
Oscillation Circuit (OSC)
The HD66760 can provide R-C oscillation simply through the addition of an external oscillation-resistor
between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size,
and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be
supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be
reduced. For details, see the Oscillation Circuit section.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 80 common signal drivers (COM1 to COM80) and 312
segment signal drivers (SEG1 to SEG312). When the number of lines are selected by a program, the required
common signal drivers automatically output drive waveforms, while the other common signal drivers
continue to output unselected waveforms.
Display pattern data is latched when 312-bit data has arrived. The latched data then enables the segment
signal drivers to generate drive waveform outputs. The shift direction of 312-bit data can be changed by the
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