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Si3011 Schematic ( PDF Datasheet ) - Silicon Laboratories

Teilenummer Si3011
Beschreibung PROGRAMMABLE VOICE DAA SOLUTIONS
Hersteller Silicon Laboratories
Logo Silicon Laboratories Logo 




Gesamt 30 Seiten
Si3011 Datasheet, Funktion
Si3050+Si3011/18/19
PROGRAMMABLE VOICE DAA SOLUTIONS
Features
PCM highway data interface
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
Applications
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
DECT base stations
Description
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
Functional Block Diagram
Ordering Information
See page 106.
Package Options
Si3050
CS 1
FSYNC 2
PCKLK 3
DTX 4
DRX 5
RGDT 6
Si3050
Top View
GND
18 GND
17 VDD
16 VA
15 C1A
14 C2A
13 RESET
Si3011/18/19
CS
SCLK
SDI
SDO
SDI THRU
PCLK
DTX
DRX
FSYNC
RGDT
RG
TGD
TGDE
RESET
AOUT/INT
Si3050
Control
Data
Interface
Line
Data
Interface
Isolation
Interface
Control
Logic
Si3018/19
Isolation
Interface
Hybrid, AC
and DC
Terminations
Ring Detect
Off-Hook
RX
IB
SC
DCT
VREG
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
NC 1 20 19 18 17 16
RX 2
15 DCT3
IB 3
C1B 4
IGND
PAD
14 QB
13 QE2
C2B 5
12 SC
6 7 8 9 10 11 NC
US Patent# 5,870,046
US Patent# 6,061,009
Rev. 1.5 10/11
Copyright © 2011 by Silicon Laboratories
Si3050 + Si3011/18/19






Si3011 Datasheet, Funktion
Si3050 + Si3011/18/19
Table 2. Loop Characteristics
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, see Figure 1 on page 6)
Parameter
Symbol
Test Condition
Min Typ Max Unit
DC Termination Voltage
DC Termination Voltage
VTR IL = 20 mA, ILIM = 0 — — 6.0 V
DCV = 00, MINI = 11, DCR = 0
VTR IL = 120 mA, ILIM = 0 9
DCV = 00, MINI = 11, DCR = 0
——
V
DC Termination Voltage
DC Termination Voltage
DC Termination Voltage
VTR IL = 20 mA, ILIM = 0 — — 7.5 V
DCV = 11, MINI = 00, DCR = 0
VTR IL = 120 mA, ILIM = 0 9
DCV = 11, MINI = 00, DCR = 0
——
V
VTR IL = 20 mA, ILIM = 1 — — 7.5 V
DCV = 11, MINI = 00, DCR = 0
DC Termination Voltage
DC Termination Voltage
On-Hook Leakage Current
Operating Loop Current
Operating Loop Current
DC Ring Current
Ring Detect Voltage*
Ring Detect Voltage*
Ring Detect Voltage*
Ring Frequency
Ringer Equivalence Number
VTR
VTR
ILK
ILP
ILP
VRD
VRD
VRD
FR
REN
IL = 60 mA, ILIM = 1
DCV = 11, MINI = 00, DCR = 0
IL = 50 mA, ILIM = 1
DCV = 11, MINI = 00, DCR = 0
VTR = –48 V
MINI = 00, ILIM = 0
MINI = 00, ILIM = 1
dc current flowing through ring
detection circuitry
RT2 = 0, RT = 0
RT2 = 0, RT = 1
RT2 = 1, RT = 1
40
10
10
13.5
19.35
40.5
13
1.5
15
21.5
45
—V
40 V
5 µA
120 mA
60 mA
3 µA
16.5
23.65
49.5
68
0.2
Vrms
Vrms
Vrms
Hz
*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected
above the maximum.
TIP
+
600
Si3011/18/19 VTR
10F
RING
Figure 1. Test Circuit for Loop Characteristics
IL
6 Rev. 1.5

6 Page









Si3011 pdf, datenblatt
Si3050 + Si3011/18/19
Table 8. Switching Characteristics—PCM Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Symbol
Test
Conditions
Min
Typ Max Units
Cycle Time PCLK
tp
122
3906
ns
Valid PCLK Inputs
— 256 — kHz
— 512 — kHz
— 768 — kHz
1.024
— MHz
1.536
— MHz
2.048
— MHz
4.096
— MHz
8.192
— MHz
FSYNC Period2
tfp — 125 — s
PCLK Duty Cycle
tdty 40 50 60 %
PCLK Jitter-Tolerance
tjitter
— — 2 ns
FSYNC Jitter Tolerance
tjitter
±120
ns
Rise Time, PCLK
tr — — 25 ns
Fall Time, PCLK
tf — — 25 ns
Delay Time, PCLK Rise to DTX Active
td1
— — 20 ns
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tri-State3
td2
td3
— — 20 ns
— — 20 ns
Setup Time, FSYNC Rise to PCLK Fall
tsu1
25 — — ns
Hold Time, PCLK Fall to FSYNC Fall
th1
20 — — ns
Setup Time, DRX Transition to PCLK Fall
tsu2
25 — — ns
Hold Time, PCLK Falling to DRX Transition
th2
20 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
PCLK
tsu1
FSYNC
tp
th1
t fp
DRX
td1
tsu2 th2
td2
td3
DTX
Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)
12 Rev. 1.5

12 Page





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