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Número de pieza | TX43D50VM0BAA | |
Descripción | TFT Module | |
Fabricantes | Hitachi | |
Logotipo | ||
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FOR MESSRS:
DATE : May 31st ,2012
CUSTOMER’S ACCEPTANCE SPECIFICATIONS
TX43D50VM0BAA
Contents
No. ITEM
1 COVER
2 RECORD OF REVISION
3 GENERAL DATA
4 ABSOLUTE MAXIMUM RATINGS
5 ELECTRICAL CHARACTERISTICS
6 OPTICAL CHARACTERISTICS
7 BLOCK DIAGRAM
8 INTERFACE PIN ASSIGNMENT
9 TIMING CHART
10 OUTLINE DIMENSIONS
11 APPEARANCE STANDARD
12 PRECAUTIONS
13 DESIGNATION OF LOT MARK
SHEET No.
7B64PS 2701-TX43D50VM0BAA-1
7B64PS 2702-TX43D50VM0BAA-1
7B64PS 2703-TX43D50VM0BAA-1
7B64PS 2704-TX43D50VM0BAA-1
7B64PS 2705-TX43D50VM0BAA-1
7B64PS 2706-TX43D50VM0BAA-1
7B64PS 2707-TX43D50VM0BAA-1
7B64PS 2708-TX43D50VM0BAA-1
7B64PS 2709-TX43D50VM0BAA-1
7B64PS 2710-TX43D50VM0BAA-1
7B64PS 2711-TX43D50VM0BAA-1
7B64PS 2712-TX43D50VM0BAA-1
7B64PS 2713-TX43D50VM0BAA-1
PAGE
1-1/1
2-1/1
3-1/2~2/2
4-1/1
5-1/2~2/2
6-1/2~2/2
7-1/1
8-1/5~5/5
9-1/4~4/4
10-1/2~2/2
11-1/3~3/3
12-1/1~2/2
13-1/1
ACCEPTED BY:
PROPOSED BY:
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
7B64PS 2701-TX43D50VM0BAA-1
PAGE 1-1/1
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4. ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Input Voltage of Logic
Operating Temperature
Storage Temperature
Backlight Input Voltage
Symbol
VDD
VI
Top
Tst
VLED
Min.
0
-0.3
0
-20
-
Max.
6
3.4
50
60
(18)
Unit
V
V
$C
$C
V
Remarks
-
Note 1
Note 2
Note 2
-
Note 1: It is applied to LVDS signal.
Note 2: Temperature and Humidity should be applied to the center glass surface of TFT module, not
to the system installed with a module. The temperature at the center of rear surface should be
less than 60°C on the condition of operating. Function of module is guaranteed in above
operating temperature range, but optical characteristics is specified for only 25°C operating
condition.
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
7B64PS 2704-TX43D50VM0BAA-1
PAGE 4-1/1
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8. INTERFACE PIN ASSIGNMENT
8.1 TFT-LCD MODULE
CN1: JAE: FI-X30SSLA-HF or Equivalent
(Matching connector: JAE: FI-X30HL or FI-X30C2L-NPB or Equivalent)
Pin No.
Symbol
Function
1 VDD
2 VDD
Power Supply (+5.0V)
3 VDD
4 VDD
5 VSS
6 VSS
GND (0V)
7 VSS
8 VSS
9
TEST1
Test Pin (OPEN)
10
TEST2
Test Pin (OPEN)
11
VSS
GND (0V)
12 RX0-
Pixel Data
13 RX0+
14
VSS
GND (0V)
15 RX1-
Pixel Data
16 RX1+
17
VSS
GND (0V)
18 RX2-
Pixel Data
19 RX2+
20
VSS
GND (0V)
21 CLK-
Pixel Clock
22 CLK+
23
VSS
GND (0V)
24 RX3-
Pixel Data
25 RX3+
26 VSS GND (0V)
27
AMODE
LVDS Mode Select
28
TEST3
Test Pin (OPEN)
29
TEST4
Test Pin (OPEN)
30
VSS
GND (0V)
Notes 1) All Vss pins should be grounded.
2) RXn- and RXn+ (n=0,1,2,3), CLK- and CLK+ should be wired by twist-pairs
or side-by-side FPC patterns, respectively.
3) Please keep open.
4) All VDD pins should be connected to +50 V (typ.).
5) Please refer to page 8-4/5 "LVDS interface" for LVDS data mapping.
Note
4
1)
3)
3)
1)
2)
1)
2)
1)
2)
1)
2)
1)
2)
1)
5)
3)
3)
1)
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
7B64PS 2708-TX43D50VM0BAA-1
PAGE 8-1/5
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11 Page |
Páginas | Total 27 Páginas | |
PDF Descargar | [ Datasheet TX43D50VM0BAA.PDF ] |
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