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TX41D97VC1HAA Schematic ( PDF Datasheet ) - Hitachi
| Teilenummer | TX41D97VC1HAA |
|
| Beschreibung | TFT Module | |
| Hersteller | Hitachi | |
| Logo |  |
|
Gesamt 15 Seiten 
Global LCD Panel Exchange Center
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ᶧ᥏؛␜࡙࠾࠶࠻ࢬ᭽ᦠ
LCD Unit Purchase Specification
ውዊઑ↪(Scope) ᧄ᭽ᦠߪ, ਅܕߩᶧ᥏؛␜࡙࠾࠶࠻ߩࢬߦઑ↪ߔࠆዊ
These specifications apply to LCD units that can be used in information
processing equipment and related equipment.
ݕᒰຠ(Item Number)
‛ຠ⇟ภ
ፌጪጰ
(Item Number) (Manufacturer)
ፌጪጰ ဳᩰ
Ę
(manufacturer's part number) (remarks)
CP76732-0
˰ᣣ┙࠺ࠖࠬࡊࠗ࠭ TX4D97VCGAAዋ
Hitachi Displays, ʲTX4D97VCHAA
Ltd.
6."SXGA+/TFT-LCD
LVDS-2ch
ዎዊ᭴߮․ᕈ(Characteristicd and Structure)
ᧄຠߪጞ ᰴߩฦິߦ␜ߔ᭴߮․ᕈࠍߔࠆߎߣ.
The product shall possess the characteristics and the structure listed in the tabel below.
˨ ິ⋡(Item)
ው ᭴ወኸᴺ(Structure and dimensions)
؛ው. (Table .)
ዎ ࠗࡦ࠲ࡈࠚࠬାภଙ(Interface signal configuration) ؛ዎ. (Table 2.)
ዏ ⛘ኻᦨᄢቯᩰ(Absolute maximum ratings)
؛ዏ. (Table 3.)
ዐ ช᳇⊛․ᕈ(DC characteristics)
؛ዐ. (Table 4.)
ዑ ജାภߩ࠲ࠗࡒࡦࠣ․ᕈ(AC characteristics)
؛ዑ. (Table 5.)
ዒ ࠗࡦ࠲ࡈࠚࠬ࠲ࠗࡒࡦࠣ(Interface timing)
࿑ው. (Table .)
ዓ శቇ․ᕈ(Optical characteristics)
؛ዒ. (Table 6.)
ዔ ชḮࠪࠤࡦࠬ(Power supply sequence)
࿑ዎ. (Fig.ዎ.)
ዕ ᭴࿑(Structural drawing)
࿑ዏ. (Fig.ዏ.)
ውዌ ؛␜(marking)
ውው ጬፗጺፆጤጪጷࡉፕጩጲ࿑ (interface block diagram)
ውዎ ജାภߣࠞߩኻᔕ
(Correspondence between input signals and colors)
ውዏ ജାภߣ↹้؛␜¾(Data and display relationships)
ውዐ శቇ․ᕈߩቯå(Definition of optical characteristics)
ውዑ ᄖ۠ᬌᩏۉᩰ(Display appearance requirements)
ውዒ ⅣႺ᧦ઙ(Environmental resistance characteristics)
ውዓ ᪿ൮⁁ᘒߢߩĤؓ᠄ۉᩰ
(Package impact resistance requirements)
TFT-LCD ፏፀጩጾࢬ᭽ᦠߩౝኈ
ࠍḩࣧߔࠆߎߣ(CP006566-0 03 )
As specified by the Fujitsu
Standard "TFT-LCD Unit Purchase
Common purchase Specification"
(CP006566-0 Rev.03).
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ዷTable 2 Interface signal configuration]
ዎዉው ደዢደᶧ᥏ࡄࡀ࡞ྏേૡ(TFT LCD Panel Driving Section)
ࠦࡀࠢ࠲ࡔࠞ(Connector manufacturer) : ᣣᧄɦⓨชሶ(JAE)߹ߚߪ⋧ᒰຠ
↪ࠦࡀࠢ࠲(Connector used in this LCD): FI-XB30S-HF0 or equivalent
ઑวࠦࡀࠢ࠲(Mating connector)
:
Pin ˨ ܕภ
(Symbol)
ᯏƫ(Function)
ᭂᕈ
(Polarity)
Vss
Ground
2 Vcc
+3.3ዲชḮ(+3.3V power supply)
3 Vcc
+3.3ዲชḮ(+3.3V power supply)
4 Vss
Ground
5 Vss
Ground
6 Vss
Ground
7 Vss
Ground
8 IN0- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
9 IN0+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
0 Vss
Ground
IN- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
2 IN+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
3 Vss
Ground
4 IN2- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
5 IN2+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
6 Vss
Ground
7 CLKIN- ጲፕጩጲାภ(-)(clock data(-))
8 CLKIN+ ጲፕጩጲାภ(+)(clock data(+))
9 Vss
Ground
20 2IN0- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
2 2IN0+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
22 Vss
Ground
23 2IN- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
24 2IN+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
25 Vss
Ground
26 2IN2- ↹⚛࠺ጪጺାภ(-)(pixel data(-))
27 2IN2+ ↹⚛࠺ጪጺାภ(+)(pixel data(+))
28 Vss
Ground
29 2CLKIN- ጲፕጩጲାภ(-)(clock data(-))
30 2CLKIN+ ጲፕጩጲାภ(+)(clock data(+))
P 30P
ᯓ
Viewing From
Display side.
ޣውޤ࡙࠾࠶࠻ߩዢዣዉዯዣ߇࡙࠾࠶࠻ౝૡߢߦធ⛯ߐࠇߡࠆߎߣޕ
Flame ground and Signal ground must be connected together in this unit.
ዎዉዎ ࡃ࠶ࠢࠗ࠻ૡ(Back light Section)
ࠦࡀࠢ࠲ࡔࠞ(Manufacturer)
↪ࠦࡀࠢ࠲ (Connector used)
ઑวࠦࡀࠢ࠲ (Mating connector)
:ᣣᧄ⌕┵ሶ(JST)
:BHSR-02VS-
:SM02B-BHSS--TB
Pin ˨ ܕภ(Symbol)
0 ዲHIGH
02 ዲLOW
ᯏƫ(Function)
ࡦࡊജ┵ሶ(Lamp input terminal(high-voltage side)
ࡦࡊജ┵ሶ(Lamp input terminal(low-voltage side)
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ዑዉዏ ࠗࡦ࠲ࡈࠚࠬ࠲ࠗࡒࡦࠣ․ᕈዄInterface signal timing characteristics)
ጐዟየዧ
CLK-
CLK+
Vdiff=0V
Vdiff=0V
Rin0+
Rin0-
tpd0
tpd
tpd2
tpd3
tpd4
tpd5
tpd6
ࠗࡦ࠲ࡈࠚࠬ࠲ࠗࡒࡦࠣ(Interface timing)
ິ⋡(Item)
ܕภ(Symbol)
min
typ
max unit
DCLK ᵄᢙ(Frequency) /tclk 5 54
57 MHz
࠺࠲
¾
Data
positi
on
0⇟⋡࠺ጪጺ(0 data)
⇟⋡࠺ጪጺ( data)
2⇟⋡࠺ጪጺ(2 data)
3⇟⋡࠺ጪጺ(3 data)
4⇟⋡࠺ጪጺ(4 data)
5⇟⋡࠺ጪጺ(5 data)
6⇟⋡࠺ጪጺ(6 data)
tpd0
tpd
tpd2
tpd3
tpd4
tpd5
tpd6
-0.49
/7tclk-0.49
2/7tclk-0.49
3/7tclk-0.49
4/7tclk-0.49
5/7tclk-0.49
6/7tclk-0.49
0
/7tclk
2/7tclk
3/7tclk
4/7tclk
5/7tclk
6/7tclk
0.49
/7tclk+0.49
2/7tclk+0.49
3/7tclk+0.49
4/7tclk+0.49
5/7tclk+0.49
6/7tclk+0.49
ns
࠺࠲ࡑ࠶ࡇࡦࠣዄData mapping)
ጐዟየዧ
CLK-
CLK+
Vdiff=0V
Vdiff=0V
Rin0+
Rin0-
ዣዌ ዮዑ ዮዐ ዮዏ ዮዎ ዮው ዮዌ
Rin+
Rin-
ዞው ዞዌ ዣዑ ዣዐ ዣዏ ዣዎ ዣው
Rin2+
Rin2-
ENA Vs Hs ዞዑ ዞዐ ዞዏ ዞዎ
೨ᦼ
ውዟየዧᦼಽߩାภ
ᰴߩᦼ
Previous cycle
Signals in one DCLK cycle
Next cycle
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| Seiten | Gesamt 15 Seiten | |
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