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TMD54X110CBB Schematic ( PDF Datasheet ) - Hitachi
| Teilenummer | TMD54X110CBB |
|
| Beschreibung | TFT Module | |
| Hersteller | Hitachi | |
| Logo |  |
|
Gesamt 24 Seiten 
Hitachi Displays, Ltd.
Date; May. 29, 2009
TECHNICAL DATA
TMD54X110CBB
CONTENTS
No. Item
— COVER
— RECORD OF REVISION
— APPLICATION
— DESCRIPTION
1 ABSOLUTE MAXIMUM RATINGS
2 OPTICAL CHARACTERISTICS
3 ELECTRICAL CHARACTERISTICS
4 BLOCK DIAGRAM
5 INTERFACE PIN ASSIGNMENT
6 TIMING DIAGRAMS OF INTERFACE TIMING
7 DIMENSIONAL OUTLINE
6 DESIGNATION OF LOT MARK
7 PRECAUTION
Sheet No.
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
DPBCL0002037-1
Page
1-1/1
2-1/1
3-1/1
4-1/1
5-1/1
6-1/2 - 6-2/2
7-1/1
8-1/1
9-1/6 - 9-6/6
10-1/3 - 10-3/3
11-1/2 - 11-2/2
12-1/1
13-1/3 - 13-3/3
The information described in this technical specification is tentative and it is possible to be changed
without prior notice.
Hitachi Displays, Ltd.
Sh.
No.
DPBCL0002037-1
Page 1-1/1
 
2. OPTICAL CHARACTERISTICS
The following optical characteristics are measured when the LCD is set alone (apart from driving
circuits and monitor cabinets) and under stable conditions. It takes about 30 minutes to reach stable
conditions. The measuring point is the center of display area unless otherwise noted.
The optical characteristics should be measured in a dark room or equivalent state.
Measuring equipment: Prichard 1980A, or equivalent [N.I.S.T (Standard Source A)]
Environmental Temperature = 25°C, VDD=12.0V, fV=60Hz,
IL=7.0mA (average of 6 pieces of CFLs)
Item
Contrast Ratio
Response Rise
Time
Fall
Brightness of white
Brightness uniformity
Red
Color
Chromaticity
(CIE)
Green
Blue
White
Red
Variation of
Color Position
(CIE)
Green
Blue
White
Symbol
CR
ton
toff
Bwh
Buni
x
y
x
y
x
y
x
y
∆x
∆y
∆x
∆y
∆x
∆y
∆x
∆y
Contrast Ratio at 85° CR85°
Condition
θ = 0°
1)
θ = +50°
φ = 0°, 90°
180°, 270°
1)
θ = +85°
φ = 0°, 90°
180°, 270° 1)
Min.
300
—
—
220
—
0.61
0.30
0.26
0.57
0.12
0.03
0.28
0.30
—
—
—
—
—
—
—
—
10
Typ.
550
16
14
280
—
0.64
0.33
0.29
0.60
0.15
0.06
0.31
0.33
—
—
—
—
—
—
—
—
—
Max.
—
20
19
—
25
0.67
0.36
0.32
0.63
0.18
0.09
0.34
0.36
0.04
0.04
0.04
0.04
0.04
0.04
0.04
0.04
Unit
—
ms
cd/m2
%
Note
2)
3)
—
4)
— Gray scale
= 255
5)
—
Gray scale
= 255
——
—
Hitachi Displays, Ltd.
Date May. 29, 2009
Sh.
No.
DPBCL0002037-1
Page 6-1/2
6 Page 
BLOCK DIAGRAM OF INTERFACE
System (PC) side
LVDS Transceiver
TAIN
RA0~RA7
GA0~GA7
BA0~BA7
1)
(Reserved)
(Reserved)
DTMG
CN1
RAIN0+
RAIN0-
RAIN1+
RAIN1-
RAIN2+
RAIN2-
RAIN3+
RAIN3-
Super-TFT module side
LVDS Receiver
RAOUT
RA0~RA7
GA0~GA7
BA0~BA7
DTMG
Host
Graphics
Controller
PLL
ODD pixel
TBIN
RB0~RB7
GB0~GB7
BB0~BB7
1)
(Reserved)
(Reserved)
(Reserved)
LVDS Transceiver
RCLKAIN+
RCLKAIN-
CN2
RBIN0+
RBIN0-
RBIN1+
RBIN1-
RBIN2+
RBIN2-
RBIN3+
RBIN3-
PLL
ODD pixel
LVDS Receiver
RBOUT
RB0~RB7
GB0~GB7
BB0~BB7
(Reserved)
(Reserved)
(Reserved)
PLL
EVEN pixel
RCLKBIN+
RCLKBIN-
PLL
EVEN pixel
LCD Panel
Controller
RA0~7, RB0~7 : R data
GA0~7, GB0~7 : G data
BA0~7, BB0~7 : B data
DTMG
: Display timing data
Receiver: Equivalent of THC63LVDF84B by THine
Notes 1) RSVD (reserved) pins on a transmitter should be connected with Vss.
2) The system must have a LVDS transmitter to drive a module.
3) The impedance of LVDS cable should be 50 ohms per a signal line or about 100 ohms per
a twist-pair line when it is used differentially.
Hitachi Displays, Ltd.
Date May. 29, 2009
Sh.
No.
DPBCL0002037-1
Page 9-3/6
12 Page | ||
| Seiten | Gesamt 24 Seiten | |
| PDF Download | [ TMD54X110CBB Schematic.PDF ] | |
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