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Si5317 Schematic ( PDF Datasheet ) - Silicon Laboratories
| Teilenummer | Si5317 |
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| Beschreibung | PIN-CONTROLLED 1-711 MHZ JITTER CLEANING CLOCK | |
| Hersteller | Silicon Laboratories | |
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Gesamt 30 Seiten 
Si5317
PIN-CONTROLLED 1–711 MHZ JITTER CLEANING CLOCK
Features
Provides jitter attenuation for any clock Selectable output clock signal
frequency
format: LVPECL, LVDS, CML or
One clock input / two clock outputs
CMOS
Input/output frequency range:
Single supply: 1.8, 2.5, or 3.3 V
1–711 MHz
Loss of lock and loss of signal
Ultra low jitter: 300 fs
alarms
(12 kHz–20 MHz) typical
VCO freeze during LOS/LOL
Simple pin control interface
On-chip voltage regulator with high
Selectable loop bandwidth for jitter
PSRR
attenuation: 60 Hz–8.4 kHz
Small size: 6 x 6 mm, 36-QFN
Meets OC-192 GR-253-CORE jitter Wide temperature range: –40 to
specifications
+85 ºC
Applications
Data converter clocking
Wireless infrastructure
Networking, SONET/SDH
Switches and routers
Medical instrumentation
Test and measurement
Description
The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications
that require jitter attenuation without clock multiplication. The Si5317 accepts a
single clock input ranging from 1 to 711 MHz and generates two low jitter clock
outputs at the same frequency. The clock frequency range and loop bandwidth are
selectable from a simple look-up table. The Si5317 is based on Silicon
Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation
on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The DSPLL loop bandwidth is user
selectable, providing jitter performance optimization at the application level.
Functional Block Diagram
Ordering Information:
See page 40.
Pin Assignments
Rev. 1.1 4/11
Copyright © 2011 by Silicon Laboratories
Si5317
 
Si5317
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min Typ Max Units
Input Voltage High
VIH
Input Low Current
Input High Current
Weak Internal Input Pull-up
Resistor
IIL
IIH
RPUP
VDD = 1.89 V
VDD = 2.25 V
VDD = 3.63 V
1.4 —
1.8 —
2.5 —
——
——
— 75
—
—
—
50
50
—
V
V
V
μA
μA
k
Weak Internal Input
Pull-down Resistor
RPDN
— 75 —
k
3-Level Input Pins
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
VILL
VIMM
VIHH
IILL2
IIMM2
IIHH2
— — 0.15 x VDD
0.45 x VDD — 0.55 x VDD
0.85 x VDD —
—
–20 —
—
–2 —
2
— — 20
V
V
V
μA
μA
μA
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
6 Rev. 1.1
6 Page 
Si5317
Table 4. AC Characteristics (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
LVCMOS Output Pins
Rise/Fall Times
tRF
CLOAD = 20 pf
—
See Figure 2
LOSn Trigger Window
LOSTRIG
Time to Clear LOL after LOS Cleared tCLRLOL
From last CKIN to LOS
fin unchanged and XA/XB
stable.
LOS to LOL
—
PLL Performance
Lock Time
Closed Loop Jitter Peaking
Jitter Tolerance
tLOCKHW Whenever RST, FRQTBL,
RATE, BWSEL, or FRQSEL
are changed, with valid CKIN
to LOL; BW = 100 Hz
JPK
JTOL
BW determined by
BWSEL[1:0]
—
—
5000/
BW
Minimum Reset Pulse Width
Spurious Noise
tRSTMIN
SPSPUR
Max spur @ n x f3
(n > 1, n x f3 < 100 MHz)
1
—
Phase Change due to Temperature
Variation
tTEMP
Max phase changes from
–40 to +85 ºC
—
Typ
25
—
10
0.05
—
—
–93
300
Max Units
— ns
750 μs
— ms
1.2 sec
0.1 dB
— ns pk-
pk
— μs
–70 dBc
500 ps
Table 5. Performance Specifications1, 2, 3, 4, 5
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Symbol
Jitter Generation
fIN = fOUT = 622.08 MHz,
LVPECL output format
BW = 120 Hz
JGEN
Phase Noise
fIN = fOUT = 622.08 MHz
LVPECL output format
CKOPN
Test Condition
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
Min Typ Max Unit
— 0.32 0.42 ps rms
— 0.31 0.41 ps rms
— 0.4 0.45 ps rms
—
–106
–87 dBc/Hz
—
–121
–100 dBc/Hz
—
–132
–104 dBc/Hz
—
–132
–119 dBc/Hz
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 22.
2. 114.285 MHz 3rd OT crystal used as XA/XB input.
3. VDD = 2.5 V
4. TA = 85 °C
5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20-80%), LVPECL clock output.
12 Rev. 1.1
12 Page | ||
| Seiten | Gesamt 30 Seiten | |
| PDF Download | [ Si5317 Schematic.PDF ] | |
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