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FOD3120 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FOD3120
Beschreibung Gate Drive Optocoupler
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 22 Seiten
FOD3120 Datasheet, Funktion
October 2009
FOD3120
High Noise Immunity, 2.5A Output Current,
Gate Drive Optocoupler
Features
High noise immunity characterized by 35kV/µs
minimum common mode rejection
2.5A peak output current driving capability for most
1200V/20A IGBT
Use of P-channel MOSFETs at output stage enables
output voltage swing close to the supply rail
Wide supply voltage range from 15V to 30V
Fast switching speed
– 400ns max. propagation delay
– 100ns max. pulse width distortion
Under Voltage LockOut (UVLO) with hysteresis
Extended industrial temperate range, -40°C to 100°C
temperature range
Safety and regulatory approved
– UL1577, 5000 VRMS for 1 min.
– IEC60747-5-2
RDS(ON) of 1(typ.) offers lower power
dissipation
>8.0mm clearance and creepage distance
(option ‘T’ or ‘TS’)
1,414V Peak Working Insulation Voltage (VIORM)
Applications
Industrial inverter
Uninterruptible power supply
Induction heating
Isolated IGBT/Power MOSFET gate drive
Description
The FOD3120 is a 2.5A Output Current Gate Drive
Optocoupler, capable of driving most 1200V/20A
IGBT/MOSFET. It is ideally suited for fast switching
driving of power IGBT and MOSFETs used in motor
control inverter applications, and high performance
power system.
It utilizes Fairchild’s proprietary coplanar packaging
technology, Optoplanar®, and optimized IC design to
achieve high noise immunity, characterized by high
common mode rejection.
It consists of a gallium aluminum arsenide (AlGaAs) light
emitting diode optically coupled to an integrated circuit
with a high-speed driver for push-pull MOSFET output
stage.
Related Resources
FOD3150, 1A Output Current, Gate Drive
Optocoupler Datasheet
www.fairchildsemi.com/products/opto/
Functional Block Diagram
Package Outlines
NC 1
ANODE 2
8 VCC
7 VO2
8
CATHODE 3
6 VO1
NC 4
5 VEE
Note:
A 0.1µF bypass capacitor must be connected between pins 5 and 8.
©2003 Fairchild Semiconductor Corporation
FOD3120 Rev. 1.17.0
8
11
8
1
8
1
www.fairchildsemi.com






FOD3120 Datasheet, Funktion
Switching Characteristics
Apply over all recommended conditions, typical value is measured at VCC = 30V, VEE = Ground, TA = 25°C
unless otherwise specified.
Symbol
Parameter
Conditions
tPHL
tPLH
PWD
PDD
(Skew)
tr
tf
tUVLO ON
tUVLO OFF
| CMH |
| CML |
Propagation Delay Time to Logic
Low Output
Propagation Delay Time to Logic
High Output
Pulse Width Distortion,
| tPHL – tPLH |
Propagation Delay Difference
Between Any Two Parts or
Channels, (tPHL – tPLH)(7)
Output Rise Time (10% – 90%)
Output Fall Time (90% – 10%)
UVLO Turn On Delay
UVLO Turn Off Delay
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
IF = 7mA to 16mA,
Rg = 10, Cg =10nF,
f = 10kHz, Duty Cycle = 50%
IF = 10mA , VO > 5V
IF = 10mA , VO < 5V
TA = 25°C, VCC = 30V,
IF = 7 to 16mA, VCM = 2000V(8)
TA = 25°C, VCC = 30V, VF = 0V,
VCM = 2000V(9)
Min.
150
150
-250
35
35
Typ.
275
255
20
60
60
1.6
0.4
50
50
Max. Units
400 ns
400 ns
100 ns
250 ns
ns
ns
µs
µs
kV/µs
kV/µs
Notes:
1. Maximum pulse width = 10µs, maximum duty cycle = 1.1%
2. Derate linearly above 87°C, free air temperature at a rate of 0.77mW/°C
3. No derating required across temperature range.
4. Functional operation under these conditions is not implied. Permanent damage may occur if the device is
subjected to conditions outside these ratings.
5. Device is considered a two terminal device: Pins 2 and 3 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
6. 5,000 VRMS for 1 minute duration is equivalent to 6,000 VACRMS for 1 second duration.
7. The difference between tPHL and tPLH between any two FOD3120 parts under same test conditions.
8. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of
the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. VO > 15.0V).
9. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of
the common pulse signal, Vcm, to assure that the output will remain low (i.e. VO < 1.0V).
10. Pulse Width, PW 1µs, 300pps
11. Exponential Waveform, IO(PEAK) | 2.5A | (0.3µs)
©2003 Fairchild Semiconductor Corporation
FOD3120 Rev. 1.17.0
6
www.fairchildsemi.com

6 Page









FOD3120 pdf, datenblatt
Test Circuit (Continued)
1
IF = 7 to 16mA
2
3
4
8
7 0.1µF
+
VCC = 15 to 30V
6 VO
100mA
5
Figure 22. VOH Test Circuit
18
100mA
27
0.1µF
+
VCC = 15 to 30V
3 6 VO
45
Figure 23. VOL Test Circuit
©2003 Fairchild Semiconductor Corporation
FOD3120 Rev. 1.17.0
12
www.fairchildsemi.com

12 Page





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