NT5CB256M4AN Schematic ( PDF Datasheet ) - Nanya

Teilenummer	NT5CB256M4AN
Beschreibung	1Gb DDR3 SDRAM A-Die
Hersteller	Nanya
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Gesamt 30 Seiten 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  1.5V ± 0.075V (JEDEC Standard Power Supply)  8 Internal memory banks (BA0- BA2)  Differential clock input (CK, )  Programmable  Latency: 5, 6, 7, 8, 9  Programmable Additive Latency: 0, CL-1, CL-2  Programmable Sequential / Interleave Burst Type  Programmable Burst Length: 4, 8  8 bit prefetch architecture  Output Driver Impedance Control  Write Leveling  OCD Calibration  Dynamic ODT (Rtt_Nom & Rtt_WR)  Auto Self-Refresh  Self-Refresh Temperature  Partial Array Self-Refresh  RoHS Compliance  Packages: 78-Ball BGA for x4 & x8 components 96-Ball BGA for x16 components Description The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM. The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.75V power supply and are available in BGA packages. REV 1.2 01 / 2009 1 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Type Function On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS# and DM/TDQS, NU/TDQS# ODT Input (when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal. The ODT pin will be ignored if MR1and MR2 are programmed to disable RTT.  Input Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5V ± 0.075V VDD Supply Power Supply: 1.5V ± 0.075V VSSQ Supply DQ Ground Vss Supply Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. Note: Input only pins (BA0-BA2, A0-A13, , , , , CKE, ODT, and ) do not supply termination. DDR3 SDRAM Addressing Configuration NT5CB256M4AN NT5CU128M8AN NT5CB64M16AP # of Bank 888 Bank Address BA0 – BA2 BA0 – BA2 BA0 – BA2 Auto precharge A10 / AP A10 / AP A10 / AP BL switch on the fly A12 /  A12 /  A12 /  Row Address A0 – A13 A0 – A13 A0 – A12 Column Address A0 – A9, A11 A0 – A9 A0 – A9 Page size 1KB 1KB 2KB Note: Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: Page size = 2 COLBITS * ORG / 8 COLBITS = the number of column address bits ORT = the number of I/O (DQ) bits REV 1.2 01 / 2009 6 6 Page 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Register Definition Programming the Mode Registers For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. CK CK CMD MRS ADDR VAL NOP NOP tMRD NOP NOP MRS VAL CKE Do not Care Time break The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following figure. CK CK CMD MRS ADDR VAL NOP NOP tMOD NOP NOP Non MRS VAL CKE Old Setting Updating Setting VAL New Setting The mode register contents can be changed using the same command and timing requirements during normal operation as long as 12 REV 1.2 01 / 2009 12 Page
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Teilenummer	Beschreibung	Hersteller
NT5CB256M4AN	1Gb DDR3 SDRAM A-Die	Nanya

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