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NT5CB128M8FN-DH Schematic ( PDF Datasheet ) - Nanya
| Teilenummer | NT5CB128M8FN-DH |
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| Beschreibung | 1Gb SDRAM | |
| Hersteller | Nanya | |
| Logo |  |
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Gesamt 30 Seiten 
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Nanya Technology Corp.
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 10-10-10,11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
1Gb
(Org. / Package)
Length x Width Ball pitch
(mm)
(mm)
128Mbx8
78-ball
TFBGA
8.00 x 10.50
0.80
64Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Density and Addressing
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tREFI(us) 5
tRFC(ns) 6
128Mb x 8
64Mb x 16
BA0 – BA2
BA0 – BA2
A10 / AP
A12 /
A10 / AP
A12 /
A0 – A13
A0 – A9
A0 – A12
A0 – A9
1KB 2KB
Tc<=85℃:7.8, Tc>85℃:3.9
110ns
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE 7
Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
The timing specification of high speed bin is backward compatible with low speed bin.
Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional and
unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
Violating tRFC specification will induce malfunction.
Only Support prime DQ’s feedback for each byte lane. Please contact with NTC for the feedback of all DQs which is enabled by using an electrical fuse.
Version 1.4
02/2014
1 Nanya Technology Cooperation ©
NTC has the rights to change any specifications or product without notification.
All Rights Reserved.
 
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
Ball Configuration – 78 Ball BGA Package (X8)
<TOP View>
See the balls through the package
1
A VSS
B VSS
C VDDQ
D VSSQ
E VREFDQ
F NC
G ODT
H NC
J VSS
K VDD
L VSS
M VDD
N VSS
1
2
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
BA0
A3
A5
A7
REET
2
3
NC
DQ0
DQS
DQ4
RA
A
WE
BA2
A0
A2
A9
A13
3
456
7
NU,T
DM,TDQS
DQ1
VDD
DQ7
CK
A10/AP
NC
A12,
A1
A11
NC
456
7
8
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
9
A
B
C
D
E
F
G
H
J
K
L
M
N
Unit: mm
* BSC (Basic Spacing between Center)
Version 1.3
09/ 2013
6 Nanya Technology Cooperation ©
All Rights Reserved.
6 Page 
DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP
“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,
including expiration of tDLLK and tZQinit.
4. The DDR3(L) DRAM will keep its on-die termination in high impedance state as long as REETis asserted. Further,
the DRAM keeps its on-die termination in high impedance state after REET de-assertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the
ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command
to load mode register. [TXPR=max (tXS, 5tCK)]
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,
provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 (L) SDRAM is now ready for normal operation.
Version 1.3
09/ 2013
12 Nanya Technology Cooperation ©
All Rights Reserved.
12 Page | ||
| Seiten | Gesamt 30 Seiten | |
| PDF Download | [ NT5CB128M8FN-DH Schematic.PDF ] | |
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