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SF1530 Schematic ( PDF Datasheet ) - SiFirst
| Teilenummer | SF1530 |
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| Beschreibung | High Performance Current Mode PWM Controller | |
| Hersteller | SiFirst | |
| Logo |  |
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Gesamt 11 Seiten 
SF1530
High Performance Current Mode PWM Controller
FEATURES
◆ Proprietary “Zero OCP/OPP Recovery Gap”
Control
◆ Built-in Soft Start Function
◆ All Pins Floating Protection
◆ Very Low Startup Current
◆ High Voltage CMOS Process with Excellent
ESD Protection
◆ Frequency Reduction and Burst Mode Control
for Energy Saving
◆ Current Mode Control
◆ Built-in Frequency Shuffling
◆ Programmable Switching Frequency
◆ Built-in Synchronous Slope Compensation
◆ Cycle-by-Cycle Current Limiting
◆ Built-in Leading Edge Blanking (LEB)
◆ Constant Power Limiting
◆ Audio Noise Free Operation
◆ VDD OVP & Clamp
◆ VDD Under Voltage Lockout (UVLO)
APPLICATIONS
Offline AC/DC Flyback Converter for
◆ AC/DC Adaptors
◆ Open-frame SMPS
◆ Set-Top Box Power Supplies
◆ ATX Standby Power
GENERAL DESCRIPTION
SF1530 is a high performance, low cost, highly
integrated current mode PWM controller for offline
flyback converter applications.
PWM switching frequency with shuffling is externally
programmable, which can reduce conduction EMI
emission of a power supply. When the output power
demands decrease, the IC automatically decreases
switching frequency for high power conversion
efficiency. When the current set-point falls below a
given value, e.g. the output power demand
diminishes, the IC enters into burst mode and
provides excellent efficiency without audio noise.
The IC can achieve “Zero OCP/OPP Recovery Gap”
using SiFirst’s proprietary control algorithm.
Meanwhile, the OCP/OPP variation versus universal
line input is compensated.
The IC has built-in synchronized slope compensation
to prevent sub-harmonic oscillation at high PWM duty
output. The IC also has built-in soft start function to
soften the stress on the MOSFET during power on
period.
SF1530 integrates functions and protections of Under
Voltage Lockout (UVLO), VCC Over Voltage
Protection (OVP), Cycle-by-cycle Current Limiting
(OCP), All Pins Floating Protection, Over Load
Protection (OLP), RT Pin Short-to-GND Protection,
Gate Clamping, VCC Clamping, Leading Edge
Blanking (LEB).
SF1530 is available in SOT23-6, SOP-8 and DIP-8
packages.
TYPICAL APPLICATION
AC IN
65
GATE VDD
4
CS
SF1530
GND FB RT
1 23
DC Out
TL431
©SiFirst Technology
www.sifirsttech.com
-1-
SF1530_DS_V1.0
 
OPERATION DESCRIPTION
SF1530 is a high performance, low cost, highly
integrated current mode PWM controller for offline
flyback converter applications. The built-in
advanced energy saving with high level protection
features improves the SMPS reliability and
performance without increasing the system cost.
◆ UVLO and Startup Operation
Fig.1 shows a typical startup circuitn. Before the IC
begins switching operation, it consumes only
startup current (typically 5uA) and current supplied
through the startup resistor Rst charges the VDD
hold-up capacitor Cdd. When VDD reaches UVLO
turn-on voltage of 14V(typical), SF1530 begins
switching and the IC current consumed increased
to 2mA (typical). The hold-up capacitor Cdd
continues to supply VDD before the energy can be
delivered from auxiliary winding Na. During this
process, VDD must not drop below UVLO turn-off
voltage (typical 9V). The selection of Rst and Cdd
should be a trade off between the power loss and
startup time.
SF1530
◆ “Zero OCP/OPP Recovery Gap” Control
The definition of OCP or OPP recovery gap of a
power adaptor is illustrated in Fig.2. At T0,
assuming an adaptor is at full loading mode. If the
loading keeps increasing, then the system will
output maximum power P_opp, which will trigger
OPP protection at the same time. After the OPP
protection is triggered, usually the system will enter
into the auto-recovery mode, in burst manner. If the
system power demand decreases below
P_recovery, then system will enter into normal
mode again, as shown in Fig.2. The difference
between P_opp and P_recovery is defined as “OPP
Recovery Gap”, which can cause system startup
failure especially in 90VAC full load startup.
AC IN
Cbulk Rst
SF1530
1 GND GATE 6
2 FB
3 RT
VDD 5
CS 4
Cdd
Np
Na
Fig.1
◆ Low Operating Current
The operating current in SF1530 is as small as
1.3mA (typical). The small operating current results
in higher efficiency and reduces the VDD hold-up
capacitance requirement.
◆ Soft Start
SF1530 features an internal 3ms (typical) soft start
that slowly increases the threshold of cycle-by-
cycle current limiting comparator during startup
sequence. It helps to prevent transformer saturation
and reduce the stress on the secondary diode
during startup. Every restart attempt is followed by
a soft start activation.
Fig.2
SF1530 can achieve “Zero OCP/OPP Recovery
Gap” in the whole universal AC input range using
SiFirst’s proprietary control algorithm.
◆ Synchronous Slope Compensation
InSF1530, the synchronous slope compensation
circuit is integrated by adding voltage ramp onto the
current sense input voltage for PWM generation.
This greatly improves the close loop stability at
CCM and prevents the sub-harmonic oscillation
and thus reduces the output ripple voltage.
◆ Oscillator with Frequency Shuffling
Connecting a resistor from RT pin to GND
according to the equation below to program the
normal switching frequency:
FOSC (KHz)
=
6500
RT(KΩ)
It can typically operate between 50kHz to 130kHz.
To improve system EMI performance, SF1530
operates the system with ±4% frequency shuffling
around setting frequency.
◆ Leading Edge Blanking (LEB)
Each time the power MOSFET is switched on, a
turn-on spike occurs across the sensing resistor.
The spike is caused by primary side capacitance
and secondary side rectifier reverse recovery. To
avoid premature termination of the switching pulse,
©SiFirst Technology
www.sifirsttech.com
-6-
SF1530_DS_V1.0
6 Page | ||
| Seiten | Gesamt 11 Seiten | |
| PDF Download | [ SF1530 Schematic.PDF ] | |
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