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AX094F002F Schematic ( PDF Datasheet ) - Hitachi
| Teilenummer | AX094F002F |
|
| Beschreibung | IPS-Pro module | |
| Hersteller | Hitachi | |
| Logo |  |
|
Gesamt 18 Seiten 
TECHNICAL DATA
AX094F002B
CONTENTS
No. Item
- COVER
- RECORD OF REVISION
- DESCRIPTION
1 ABSOLUTE MAXIMUM RATINGS
2 INITIAL OPTICAL CHARACTERISTICS
3 ELECTRICAL CHARACTERISTICS
4 BLOCK DIAGRAM
5 INTERFACE PIN ASSIGNMENT
6 INTERFACE TIMING
Date:Mar. 29, 2007
STD-2700-1
Page
1-1/1
2-1/1
3-1/1
4-1/1
5-1/2~2/2
6-1/2~2/2
7-1/1
8-1/7~7/7
9-1/3~3/3
IPS Alpha Technology,Ltd.
Date
Mar. 29, 2007
Sheet
No.
STD2700-1
Page 1-1/1
 
Note 1) Definition of Viewing Angle
φ＝90°
（12 o'clYock）
θ＝0°
Z
θ
eye
φ＝180°X'
（9 o'clock）
φ
φ＝0°
X（3o'clock）
TFT - LCM
2) Definition of Contrast Ratio (CR)
CR=
(Luminance at displaying WHITE)
(Luminance at displaying BLACK)
Z'
Y' φ＝270°
（6 o'clock）
3) Definition of Response Time
Displaying
Data Signal
BLACK
WHITE
ton
BLACK
toff
%
Optical 100
90
Response
( Luminance)
10
0
4） Definition of Brightness Uniformit Display pattern is white (255 level) . The brightness
10% (1)
uniformity is defined as the following equation. Brightness at each
(2) (3) 50% point is measured, and average, maximum and minimum
90%
(4) (5) (6)
(7) (8) (9)
brightness is calculated.
Buni＝
Bmax or Bmin - Bave
Bave
10% 50%
90%
where, Bmax = Maximum brightness
：measuring points
Bmin = Minimum brightness
9
Σ (B(k))
Bave ＝Average brightness= k=1
×100
９
5）Variation of color position on CIE is defined as difference between colors at θ=0°and
atθ＝50°& φ=0°90°180°270°.
IPS Alpha Technology,Ltd.
Date
Mar. 29, 2007
Sheet
No.
STD2700-1
Page 5-2/2
6 Page 
5.4 LVDS INTERFACE
24bit
The 7st LVDSSEL signal of the connector pin specification is “L”.【LVDSSEL = L】
SIGNAL
TRANSMITTER
THC63LVDM83A
INTERFACE CONNECTOR
RECEIVER
TFT
CONTROL
PIN INPUT
TV Set
TFT-LCD PIN OUTPUT
INPUT
RA0/RB0
51 Tx IN0
27 Rx OUT0 RA0/RB0
RA1/RB1
52 Tx IN1
29 Rx OUT1 RA1/RB1
RA2/RB2
54 Tx IN2 TA OUT0+
Rx 0+
30 Rx OUT2 RA2/RB2
RA3/RB3
55 Tx IN3
32 Rx OUT3 RA3/RB3
RA4/RB4
56 Tx IN4
33 Rx OUT4 RA4/RB4
RA5/RB5
3 Tx IN6 TA OUT0-
Rx 0-
35 Rx OUT6 RA5/RB5
GA0/GB0
4 Tx IN7
37 Rx OUT7 GA0/GB0
GA1/GB1
6 Tx IN8
38 Rx OUT8 GA1/GB1
GA2/GB2
7 Tx IN9
39 Rx OUT9 GA2/GB2
GA3/GB3 11 Tx IN12 TA OUT1+
Rx 1+
43 Rx OUT12 RA3/RB3
GA4/GB4 12 Tx IN13
45 Rx OUT13 RA4/RB4
GA5/GB5 14 Tx IN14
46 Rx OUT14 RA5/RB5
BA0/BB0
15 Tx IN15 TA OUT1-
Rx 1-
47 Rx OUT15 RA0/RB0
BA1/BB1
19 Tx IN18
51 Rx OUT18 RA1/RB1
BA2/BB2
20 Tx IN19
53 Rx OUT19 RA2/RB2
BA3/BB3
22 Tx IN20
54 Rx OUT20 RA3/RB3
BA4/BB4
23 Tx IN21 TA OUT2+
Rx 2+
55 Rx OUT21 RA4/RB4
BA5/BB5
24 Tx IN22
1 Rx OUT22 RA5/RB5
HSYNC/RSVD1) 27 Tx IN24
3 Rx OUT24 not connect
VSYNC/RSVD1) 28 Tx IN25 TA OUT2-
Rx 2-
5 Rx OUT25 not connect
DE/RSVD1) 30 Tx IN26
6 Rx OUT26 DE/not connect
RA6/RB6
50 Tx IN27
7 Rx OUT27 RA6/RB6
RA7/RB7
2 Tx IN5
34 Rx OUT5 RA7/RB7
GA6/GB6
8 Tx IN10 TA OUT3+
Rx 3+
41 Rx OUT10 GA6/GB6
GA7/GB7 10 Tx IN11
42 Rx OUT11 GA7/GB7
BA6/BB6
16 Tx IN16
49 Rx OUT16 BA6/BB6
BA7/BB7
18 Tx IN17 TA OUT3-
Rx 3-
50 Rx OUT17 BA7/BB7
RSVD 1)
25 Tx IN23
2 Rx OUT23 RSVD 1)
DCLK
31 TxCLK IN TxCLK OUT+ RxCLK IN+ 26 RxCLK OUT DCLK
TxCLK OUT- RxCLK IN-
RA0～RA7, RB0～RB7 :Pixel R Data (7;MSB, 0;LSB)
GA0～GA7, GB0～GB7 :Pixel G Data (7;MSB, 0;LSB)
BA0～BA7, BB0～BB7 :Pixel B Data (7;MSB, 0;LSB)
DE :Data Enable
Notes 1)RSVD(reserved)pins on the transmitter shall be tied to"H"or"L".
IPS Alpha Technology,Ltd.
Date
Mar. 29, 2007
Sheet
No.
STD2700-1
Page 8-4/7
12 Page | ||
| Seiten | Gesamt 18 Seiten | |
| PDF Download | [ AX094F002F Schematic.PDF ] | |
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