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PDF HD64180 Data sheet ( Hoja de datos )
| Número de pieza | HD64180 | |
| Descripción | 8-Bit High Integration CMOS Microprocessor User Manual | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD64180 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IEC I INTEGRATED ELECTRONICS CORP.
2170 Paragon Drive
San Jose, Callfomla 95131
(408) 435-1000
1 page  
TABLE OF CONTENTS
1. HD64180 OVERViEW.................................................
1.1 Block Diagram ..................................................
1.2 Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 CPU Architecture. .. ... . . ... . ..... . . .. . ... . . . .... . . ... .. .. . .. . . . .
1.4 I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4
5
6
6
2. HD64180 HARDWARE ARCHITECTURE................................ 8
2.1 Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 CPU Bus Timing ................................................ 13
2.3 WAIT State Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
2.4 HALT and Low Power Operation Modes. . . . . . . . .. . . . .. . . . . . . . . . . .. 23
2.5 Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 26
2.6 Memory Management Unit (MMU) ............................... 30
2.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
2.8 Dynamic RAM Refresh Control ................................... 51
2.9 DMA Controller (DMAC) ....................................... 54
2.10 Asynchronous Serial Communication Interface (ASCI) .............. 68
2.11 Clocked Serial I/O Port (CSIIO) ................................... 78
2.12 Programmable Reload Timer (PRT) ............................... 84
2.13 6800 Type Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 89
2.14 On-chip Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 93
2.15 Miscellaneous................................................... 96
3. HD64180 SOFTWARE ARCHITECTURE ................................ 97
3.1 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. 97
3.2 CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 99
3.3 Addressing Modes ............................................... 102
4. HD64180 PROGRAMMING NOTE...................................... 105
5. HD64180 ELECTRICAL CHARACTERiSTiCS ............................ 120
6. HD64180 PACKAGE DIMENSiONS .................................... 132
5 Page 
1. HD64180 OVERVIEW
1.1 Block Diagram
The HD64180 combines a high performance CPU core with many of the sys-
tems and I/O resources required by a broad range of applications.
The CPU core consists of five functional blocks.
o Clock Generator
o Bus State Controller
o Interrupt Controller
o Memory Management Unit (MMU)
o Central Processing Unit (CPU)
The integrated I/O resources comprise the remaining four functional blocks.
o DMA Controller (DMAC - two channels)
o Asynchronous Serial Communication Interface (ASCI - two channels)
o Clocked Serial I/O Port (CSI/O - one channel)
o Programmable Reload Timer (PRT - two channels)
TYPE OF PRODUCTS
Type No.
HD64A1S0ROP
HD64B1S0ROP
HD64A1S0ROF
HD64B1S0ROF
HD64A1S0ROCP
HD64B1S0ROCP
Clock Frequency (MHz)
4
6
4
6
4
6
Package
DP-64S
FP-64*
CP-6S*
* Under development
3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64180.PDF ] | |
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