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RK3066 Schematic ( PDF Datasheet ) - Rockchip

Teilenummer RK3066
Beschreibung Technical Reference Manual
Hersteller Rockchip
Logo Rockchip Logo 




Gesamt 30 Seiten
RK3066 Datasheet, Funktion
RK30xxTechnical Reference ManualRev2.0
RK30xx
Technical Reference Manual
Revision 1.0
Feb. 2012
High Performance and Low-power Processor for Digital Media Application
1






RK3066 Datasheet, Funktion
RK30xxTechnical Reference ManualRev2.0
11.4.1 Register summary ........................................................324
11.4.2 Detail Register Description.............................................327
11.5 Timing Diagram...................................................................340
11.6 Interface Description ...........................................................340
11.7 Application Notes ................................................................341
Chapter 12 GIC(General Interrupt Controller)........................................342
12.1 Overview............................................................................342
12.2 Block Diagram ....................................................................342
12.3 Function Description ............................................................342
12.3.1 The Distributor.............................................................343
12.3.2 CPU interface...............................................................344
12.3.3 Interrupt handling state machine....................................344
12.4 Register Description.............................................................346
12.4.1 GIC Distributor interface register summary ......................346
12.4.2 GIC Distributor interface detail register description ...........346
12.4.3 GIC CPU interface register summary ...............................352
12.4.4 GIC CPU interface detail register description.....................352
12.5 Interface Description ...........................................................355
12.6 Application Notes ................................................................355
12.6.1 General handling of interrupts ........................................355
12.6.2 Interrupt prioritization...................................................356
12.6.3 The effect of the Security Extensions on interrupt handling.357
12.6.4 The effect of Security Extensions on interrupt priority ........358
Chapter 13 DMC (Dynamic Memory Interface).......................................360
13.1 Overview............................................................................360
13.2 Block Diagram ....................................................................361
13.3 Function description.............................................................362
13.4 DDR PHY ............................................................................363
13.4.1 DDR PHY Overview .......................................................363
13.4.2 Lane-Based Architecture................................................364
13.4.3 Master DLL(MDLL) ........................................................366
13.4.4 Master-Slave DLL(MSDLL) .............................................369
13.4.5 DQS Gating .................................................................373
13.4.6 Dynamic Strobe Drift Detection ......................................375
13.5 Register description .............................................................375
13.5.1 Registers Summary ......................................................375
13.5.2 Detail Registers Description ...........................................387
13.6 Timing Diagram...................................................................581
13.6.1 DDR3 Read/Write Access Timing.....................................581
13.6.2 LPDDR2 Read/Write Access Timing..................................582
13.7 Interface description ............................................................583
High Performance and Low-power Processor for Digital Media Application
6

6 Page









RK3066 pdf, datenblatt
RK30xxTechnical Reference ManualRev2.0
30.6 Application Notes .............................................................. 1015
Chapter 31 SDIO Host Controller ....................................................... 1016
31.1 Overview.......................................................................... 1016
31.2 Block Diagram .................................................................. 1016
31.3 Function description........................................................... 1017
31.4 Register description ........................................................... 1017
31.5 Timing Diagram................................................................. 1017
31.6 Interface description .......................................................... 1017
31.6.1 Card-Detect and Write-Protect Mechanism ..................... 1017
31.6.2 SD/MMC Controller Termination Requirement ................. 1017
31.6.3 SD/MMC Controller IOMUX........................................... 1019
31.7 Application Notes .............................................................. 1019
Chapter 32 MAC Ethernet Interface.................................................... 1020
32.1 Overview.......................................................................... 1020
32.1.1 Features ................................................................... 1020
32.2 Block Diagram .................................................................. 1020
32.2.1 Architecture............................................................... 1020
32.2.2 Frame Structure ......................................................... 1021
32.2.3 RMII Interface timing diagram...................................... 1021
32.2.4 Mangement Interface.................................................. 1022
32.3 Register description ........................................................... 1022
32.3.1 Register Summary...................................................... 1022
32.3.2 Detail Register Description........................................... 1023
32.4 Timing Diagram................................................................. 1033
32.5 Interface Description ......................................................... 1034
32.6 Application Notes .............................................................. 1035
32.6.1 Buffer Descriptors ...................................................... 1035
32.6.2 Transmit Buffer Descriptor ........................................... 1036
32.6.3 Receive Buffer Descriptor ............................................ 1038
32.6.4 Buffer Chaining .......................................................... 1040
32.6.5 Automatic Descriptor Polling ........................................ 1041
Chapter 33 High-Speed ADC /TS stream Interface ............................... 1042
33.1 Overview.......................................................................... 1042
33.1.1 Features ................................................................... 1042
33.2 Block Diagram .................................................................. 1042
33.3 Function Description .......................................................... 1043
33.4 Register Description........................................................... 1044
33.4.1 Registers Summary .................................................... 1044
33.4.2 Detail Register Description........................................... 1044
33.5 Timing Diagram................................................................. 1048
High Performance and Low-power Processor for Digital Media Application
12

12 Page





SeitenGesamt 30 Seiten
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