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HI-3113 Schematic ( PDF Datasheet ) - Holt Integrated Circuits

Teilenummer HI-3113
Beschreibung Avionics CAN Controller
Hersteller Holt Integrated Circuits
Logo Holt Integrated Circuits Logo 




Gesamt 30 Seiten
HI-3113 Datasheet, Funktion
HI-3110, HI-3111, HI-3112, HI-3113
May 2016
Avionics CAN Controller
with Integrated Transceiver
GENERAL DESCRIPTION
The HI-3110 is a standalone Controller Area Network
(CAN) controller with built in transceiver. The device
provides a complete, integrated, cost-effective solution for
avionics applications implementing the CAN 2.0B
specification and can be configured to comply with both the
ARINC 825 (General Standardization of CAN Bus Protocol
for Airborne Use) and CANaerospace standards. The HI-
3110 is capable of transmitting and receiving standard
data frames, extended data frames and remote frames.
The internal transceiver allows direct connection to the
CAN bus without using external components and coupled
with the host Serial Peripheral Interface (SPI), results in
minimal board space.
The HI-3110 provides the optimum solution for
applications where minimum host (MCU) overhead is
required, filtering unwanted messages using a maskable
identifier filter and storing up to 8 messages in the receive
FIFO. A flexible interrupt scheme allows real time
servicing of the FIFO by the host, if required.
Transmissions are handled using an 8 message transmit
FIFO. A Transmit Enable pin can be used by the host to
initiate a transmission. The device also provides monitor
or listen-only mode, low power sleep mode, loopback
mode for self-test and a re-transmission disable capability
(necessary to implement TTCAN protocol).
The HI-3111 is a digital only version of the HI-3110 (no
transceiver). This version provides a “protocol only”
solution for customers who wish to use an external
transceiver and may be used in situations where the
customer requires galvanic isolation between the bus and
digital protocol logic. The HI-3112 provides an option of a
CLKOUT pin instead of a SPLIT pin, which may be used as
the main system clock or as a clock input for other devices
in the system. Finally, the HI-3113 provides all options
(both CLKOUT and SPLIT pins) in a very compact QFN-44
package.
The HI-3110 family is available in industrial and full
extended temperature ranges, with a “RoHS compliant”
lead-free option. The design has been independently
validated by C&S group, GmbH, an ISO/IEC 17025
accredited test house. A copy of the test report is available
from Holt on request.
FEATURES
· Implements CAN version 2.0B with programmable bit
rate up to 1Mbit/sec. ISO 11898-5 compliant.
· Configurable to support ARINC 825 and
CANaerospace Standards.
· Serial Peripheral Interface (SPI) (20MHz).
· Standard, Extended and Remote frames supported.
· 8 maskable identifier filters.
· Filtering on ID and first two data bytes for both
Standard and Extended Identifiers.
· Loopback mode for self-test.
· Monitor (Listen-only) and Low Power Sleep Modes
with automatic wake-up possible.
· 8-message Transmit and Receive FIFOs.
· Internal 16-bit free running counter for time tagging of
transmitted or received messages.
· Permanent dominant timeout protection.
· Short Circuit Protection of -58V to + 58V on CAN_H,
CAN_L and SPLIT pins (ISO 11898-5).
· Re-transmission disable capability.
· Transmit Enable pin.
· Industrial and Full Extended temperature ranges
supported:
Industrial: -40oC to + 85oC.
Extended: -55oC to + 125oC.
PIN CONFIGURATION (Top View)
VLOGIC 1
OSCOUT 2
OSCIN 3
GP1 4
GP2 5
TXEN 6
SPLIT 7
GND 8
CANL 9
3110PSI
3110PST
3110PSM
18 INT
17 MR
16 CS
15 SO
14 SI
13 SCK
12 STAT
11 VDD
10 CANH
18-Pin Plastic SOIC - WB Package
(DS3110 Rev. J)
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/16






HI-3113 Datasheet, Funktion
HI-3110, HI-3111, HI-3112, HI-3113
This means that a bit stream of “1s” or “0”s appears
continuous on the bus. A logic “0” is called a dominant bit
and a logic “1” is called a recessive bit.
Bit stuffing is used to ensure frequent enough transitions
occur to achieve synchronization. Every time a transmitter
detects five consecutive bits of the same polarity in the bit
stream to be transmitted, it inserts a bit of opposite polarity
into the actual transmitted bit stream.
This bit stuffing rule applies to the Start-of-Frame field,
arbitration field, control field, data field and CRC sequence.
The CRC delimiter, ACK field and End-Of-Frame fields are of
fixed form and not stuffed (see below for definition of these
fields). Furthermore, Error frames and Overload frames are
also of fixed form and not stuffed.
An example of how the bits in a stuffed bit stream might look
is shown below.
00101011111O0000I1100000I11000
0 = dominant bit, O = dominant stuffed bit.
1 = recessive bit, I = recessive stuffed bit.
MESSAGE FRAMES
errors by computing a 15-bit CRC sequence from the
previous bit stream (SOF, arbitration field, control field and
data field, excluding stuff bits). The last bit in the CRC field is
the CRC delimiter bit (always recessive).
After the CRC field is the Acknowledge Field (ACK Field).
The first bit is the ACK Slot bit. A transmitting node sends a
recessive bit (logic 1) during the ACK slot. Any node which
receives the message error-free acknowledges the
reception by placing a dominant bit (logic 0) in the ACK slot,
over-writing the recessive bit of the transmitter. The final bit
in the ACK field is a recessive ACK delimiter bit. Therefore,
the dominant ACK slot bit is surrounded on each side by a
recessive bit.
Each data frame is delimited by an End-Of-Frame field
(EOF). The EOF consists of seven recessive bits.
Following the EOF, there is a gap to the next frame called the
Interframe Space (IFS) . The IFS consists of two bit fields,
Intermission and Bus-Idle. The Intermission consists of
three recessive bits, however the following notes apply:
a) detection of a dominant bit on the bus at the third slot is
interpreted as a SOF,
b) detection of a dominant bit in either the first or second
slots results in generation of an overload frame (see below).
STANDARD DATA FRAME
The standard data frame is shown in figure 2. The frame
starts with a Start-of-Frame (SOF) bit. This is a dominant bit
that identifies the start of the data frame on the bus.
The SOF is followed by the 12-bit arbitration field. The
arbitration field consists of an 11-bit identifer, ID28 - ID18,
and the Remote Transmission Request (RTR) bit. The RTR
bit is used to distinguish between a data frame (RTR bit
dominant, logic 0) and a remote frame (RTR bit recessive,
logic 1).
Following the arbitration field is the 6-bit control field. The
first bit of the control field is the Identifier Extension flag bit
(IDE). This is used to distinguish between standard and
extended identifiers and must be dominant (logic 0) for
standard data frames. The next bit, r0, is specified by the
CAN protocol as a reserved bit for future expansion. This bit
must be transmitted dominant, but receivers must be
capable of receiving either a dominant or recessive bit. The
final 4 bits of the control field make up the data length code
(DLC). The binary value of this 4-bit field specifies the
number of data bytes in the data payload (0 - 8 bytes). Note:
All binary combinations greater than or equal to <1 0 0 0>
specify 8 bytes of data.
After the control field is the data field, which contains a data
payload equal to the number of bytes specified by the DLC
(see note above).
The data field is followed by the 16-bit Cyclic Redundancy
Check (CRC) field. This is used to check transmission
The bus idle period is of arbitrary length and consists of
recessive bits. A dominant bit detected during this period is
interpreted as a SOF.
EXTENDED DATA FRAME
The extended data frame is shown in figure 3. In this frame
format, SOF is followed by a 32-bit arbitration field consisting
of a 29-bit identifier, ID28 - ID0. The first 11 most significant
bits of the ID are know as the base identifier. This is followed
by the Substitute Remote Request (SRR) bit, which is
defined as recessive. Following the SRR bit is the IDE bit,
which is defined as recessive for extended data frames.
Note that the SRR bit is in the same slot as the RTR bit of the
standard frame and the IDE bits are also in corresponding
slots. This means if standard and extended identifier data
frames with identical base identifiers are transmitted
simultaneously, the standard identifier data frame will win
arbitration (see Bitwise Arbitration section below).
The SRR and IDE bits are followed by the remaining 18 bits
of the identifier (extended ID) and the last bit of the
arbitration field is the RTR bit. The RTR bit has the same
function as in the standard frame format.
Following the arbitration field is the 6-bit control field. The
first two bits, r1 and r0, are specified by the CAN protocol as
reserved bits for future expansion. Both these bits must be
transmitted dominant, but receivers must be able to receive
all combinations of dominant or recessive bits. The final 4
bits of the control field is the data length code (DLC). The
binary value of this 4-bit field specifies the number of data
bytes in the data payload (0 - 8 bytes). Note: All binary
HOLT INTEGRATED CIRCUITS
6

6 Page









HI-3113 pdf, datenblatt
Overload Frame
HI-3110, HI-3111, HI-3112, HI-3113
Illegal Dominant Bit in IFS
Figure 6. Overload Frame Format
HOLT INTEGRATED CIRCUITS
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