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PDF KM29W16000ATS Data sheet ( Hoja de datos )
| Número de pieza | KM29W16000ATS | |
| Descripción | 2M x 8-Bit NAND Flash Memory | |
| Fabricantes | Samsung Electronics | |
| Logotipo |  |
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KM29W16000ATS
Document Title
2M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.1 Data Sheet 1998.
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
Remark
Preliminary
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you ha ve
any questions, please contact the SAMSUNG branch office near you.
1
1 page  
KM29W16000ATS
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable( CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable( WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable( RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling ed ge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high -z
when the chip is deselected or the outputs are disabled.
Write Protect ( WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/ Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or outputs are disabled.
Power Line(V CC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(V CC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at V CCQ.
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5 Page 
KM29W16000ATS
* Status Read Cycle
CLE
CE
WE
tCLS
tCS
tCLH
tCH
tWP
RE
I/O 0 ~ 7
tDS tDH
70H
FLASH MEMORY
tCLS
tWHR
tCSTO
tCHZ*
tIR tRSTO
tRHZ*
Status Output
READ1 OPERATION (READ ONE PAGE)
CLE
CE
WE
ALE
RE
I/O 0 ~ 7
R/B
tWB
tAR
tR
tRC
tRR
00h A0 ~ A7 A8 ~ A15 A16 ~ A20
Dout N Dout N+1 Dout N+2 Dout N+3
Column
Address
Page(Row)
Address
Busy
tCEH
tCHZ
tCRY
tRHZ
Dout 263
tRB
11
11 Page | ||
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