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AD9255 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9255
Beschreibung 1.8 V Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9255 Datasheet, Funktion
Data Sheet
14-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9255
FEATURES
SNR = 78.3 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 371 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS PDWN AGND AVDD (1.8V)
LVDS LVDS_RS
VREF
VCM
VIN+
VIN–
DITHER
CLK+
CLK–
SYNC
REFERENCE
AD9255
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC
14-BIT
14
CORE
OUTPUT
STAGING 14
CMOS OR
LVDS
(DDR)
SERIAL PORT
SVDD SCLK/ SDIO/ CSB
DFS DCS
Figure 1.
DRVDD (1.8V)
D13 TO D0
OR
OEB
DCO
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9255 Datasheet, Funktion
AD9255
Data Sheet
Parameter1
WORST OTHER (HARMONIC OR SPUR)
Without Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE SFDR
Without Dither
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
AD9255BCPZ-802 AD9255BCPZ-1052 AD9255BCPZ-1252
Temp Min Typ Max Min Typ Max Min Typ Max Unit
25°C −106
−105
−101
dBc
25°C −106
−104
−104
dBc
Full −94 −95 −91 dBc
25°C −104
−104
−103
dBc
25°C −102
−103
−100
dBc
25°C −105
−106
−101
dBc
25°C −106
−105
−104
dBc
Full −97 −99 −98 dBc
25°C −103
−103
−103
dBc
25°C −100
−101
−100
dBc
25°C 93 90 95 dBc
25°C 80 78 79 dBc
25°C 650 650 650 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 The suffix following the part number refers to the model found in the Ordering Guide section.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ Max
0.3
AGND
0.9
−100
−100
8
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
+100
+100
4
10 12
AGND
1.2
AGND
−100
−100
12
CMOS
0.9
1
16
AVDD
AVDD
0.6
+100
+100
20
Unit
V
V p-p
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
Rev. C | Page 6 of 44

6 Page









AD9255 pdf, datenblatt
AD9255
Pin No.
Mnemonic
22 D9
23 D10
24 D11
25 D12
26 D13 (MSB)
27 OR
8 DCO
SPI Control
31 SCLK/DFS
30 SDIO/DCS
32 CSB
ADC Configuration
6 OEB
35 DITHER
41 LVDS_RS
44 LVDS
48 PDWN
Data Sheet
Type
Output
Output
Output
Output
Output
Output
Output
Description
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
Overrange Output.
Data Clock Output.
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input
Input
Input
Input
Input
Output Enable Input (Active Low).
In external pin mode, this pin sets dither to on (active high). Pull low for control via
SPI in SPI mode.
In external pin mode, this pin sets LVDS reduced swing output mode (active high).
Pull low for control via SPI in SPI mode.
In external pin mode, this pin sets LVDS output mode (active high). Pull low for
control via SPI in SPI mode.
Power-down input in external pin mode. In SPI mode, this input can be configured
as power-down or standby.
Rev. C | Page 12 of 44

12 Page





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