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V500HK1-PS1 Schematic ( PDF Datasheet ) - CMI MEI

Teilenummer V500HK1-PS1
Beschreibung TFT LCD Module
Hersteller CMI MEI
Logo CMI MEI Logo 




Gesamt 30 Seiten
V500HK1-PS1 Datasheet, Funktion
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Tentative Specification
Preliminary Specification
Approval Specification
MODEL NO.: V500HK1
SUFFIX: PS1
50.0” FHD_60Hz_Open Cell
Source Board+Control Board+FFC Cable
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Approved By
Chao-Chun
Chung
Checked By
Ken Wu
Prepared By
YuYin Tsai
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V500HK1-PS1 Datasheet, Funktion
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Symbol
TST
TOP
Value
Min. Max.
-20 +60
0 50
Note (1)Temperature and relative humidity range is shown in the figure below.
Unit Note
ºC (1), (3)
ºC (1), (2), (3)
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of improper
thermal management in final product design.
Note (3) The rating of environment is base on LCD module. Leave LCD cell alone, this environment condition can’t
be guaranteed. Except LCD cell, the customer has to consider the ability of other parts of LCD module
and LCD module process.
Relative Humidity (%RH)
100
90
80
60 Operating Range
40
20
10 Storage Range
-40 -20
0 20 40 60 80
Temperature (ºC)
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V500HK1-PS1 pdf, datenblatt
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5. INPUT TERMINAL PIN ASSIGNMENT
CNF1 Connector Part No.: JAE Taiwan (؀ ᨜ ౰ ़ ሽ ՗ ) FI-RE51S-HF-CM-R1500 or equivalent.
Pin Name
Description
Note
1 VCC
Power input (+12V)
2 VCC
Power input (+12V)
3 VCC
Power input (+12V)
4 VCC
Power input (+12V)
5 VCC
Power input (+12V)
6 N.C.
No Connection
(2)
7 GND
Ground
8 GND
Ground
(6)
9 GND
Ground
10 ORX0-
Odd pixel Negative LVDS differential data input. Channel 0
11 ORX0+
Odd pixel Positive LVDS differential data input. Channel 0
12 ORX1-
13 ORX1+
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
(5)
14 ORX2-
Odd pixel Negative LVDS differential data input. Channel 2
15 ORX2+
Odd pixel Positive LVDS differential data input. Channel 2
16 GND
Ground
(6)
17 OCLK-
18 OCLK+
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input
(5)
19 GND
Ground
(6)
20 ORX3-
21 ORX3+
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
(5)
22 N.C.
23 N.C.
No Connection
No Connection
(2)
24 GND
Ground
(6)
25 ERX0-
Even pixel Negative LVDS differential data input. Channel 0
26 ERX0+
Even pixel Positive LVDS differential data input. Channel 0
27 ERX1-
28 ERX1+
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
(5)
29 ERX2-
Even pixel Negative LVDS differential data input. Channel 2
30 ERX2+
Even pixel Positive LVDS differential data input. Channel 2
31 GND
Ground
(6)
32 ECLK-
33 ECLK+
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
(5)
34 GND
Ground
(6)
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