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Teilenummer | V500DK1-P01 |
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Beschreibung | TFT LCD Module | |
Hersteller | CMI MEI | |
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Gesamt 30 Seiten PRODUCT SPECIFICATION
□ Tentative Specification
□ Preliminary Specification
■ Approval Specification
MODEL NO.: V500DK1
SUFFIX: P01
Customer:
APPROVED BY
SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your signature and
comments.
Approved By
Chao-Chun Chung
Checked By
Carlos Lee
Prepared By
Archer Chang
Version 2.0
1
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date : Jan. 18, 2013
PRODUCT SPECIFICATION
1.3 MECHANICAL SPECIFICATIONS
Item
Weight
I/F connector mounting
position
Min.
Typ.
Max.
2625
2763
2901
The mounting inclination of the connector makes the
screen center within ± 0.5mm as the horizontal.
Unit
g
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Connector mounting position
Note
-
(2)
+/- 0.5mm
Version 2.0
6
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date : Jan. 18, 2013
6 Page PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD OPEN CELL
CNF1 Connector Part No.: FCN (WF23-400-513C) or equivalent
Pin Name
Description
1 N.C.
No Connection
2 SCL
I2C Clock (for mode selection & function setting)
3 SDA
I2C Data (for mode selection & function setting)
4 N.C.
No Connection
5 L/R_O
Output signal for Left Right Glasses control
6 N.C.
No Connection
7 SELLVDS
Input signal for LVDS Data Format Selection
8 N.C.
No Connection
9 N.C.
No Connection
10 N.C.
No Connection
11 GND
Ground
12 CH1[0]-
First pixel Negative LVDS differential data input. Pair 0
13 CH1[0]+
First pixel Positive LVDS differential data input. Pair 0
14 CH1[1]-
First pixel Negative LVDS differential data input. Pair 1
15 CH1[1]+
First pixel Positive LVDS differential data input. Pair 1
16 CH1[2]-
First pixel Negative LVDS differential data input. Pair 2
17 CH1[2]+
First pixel Positive LVDS differential data input. Pair 2
18 GND
Ground
19 CH1CLK-
First pixel Negative LVDS differential clock input.
20 CH1CLK+ First pixel Positive LVDS differential clock input.
21 GND
Ground
22 CH1[3]-
First pixel Negative LVDS differential data input. Pair 3
23 CH1[3]+
First pixel Positive LVDS differential data input. Pair 3
24 CH1[4]-
First pixel Negative LVDS differential data input. Pair 4
25 CH1[4]+
First pixel Positive LVDS differential data input. Pair 4
26 2D/3D
Input signal for 2D/3D Mode Selection
27 L/R
Input signal for Left Right eye frame synchronous
28 CH2[0]-
Second pixel Negative LVDS differential data input. Pair 0
Note
(1)
(1)
(2)
(1)
(3)(9)
(1)
(4)
(4)
(4)
(5)(10)
(6)
(4)
Version 2.0
12
The copyright belongs to InnoLux. Any unauthorized use is prohibited
Date : Jan. 18, 2013
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ V500DK1-P01 Schematic.PDF ] |
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