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Teilenummer | V400HJ3-PE1 |
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Beschreibung | TFT LCD Module | |
Hersteller | CMI MEI | |
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Gesamt 30 Seiten PRODUCT SPECIFICATION
□ Tentative Specification
□ Preliminary Specification
■ Approval Specification
MODEL NO.: V400HJ3
SUFFIX: PE1
Customer: SEC
APPROVED BY
Name / Title
Note
SIGNATURE
Please return 1 copy for your confirmation with your
signature and comments.
Approved By
Checked By Prepared By
Chao-Chun Chung Josh Chi Joanne Chung
Version 2.0
1 Date:8 June. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
PRODUCT SPECIFICATION
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Value
Min. Max.
Unit Note
Storage Temperature
TST -20
+60 ºC (1)
Operating Ambient Temperature
TOP
0
50 ºC (1), (2)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta ≦ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Version 2.0
6 Date:8 June. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
6 Page PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Part No.: JAE Taiwan (台灣航空電子) FI-RE51S-HF-CM-R1500 or
equivalent.
Pin Name
Description
Note
1 VCC
Power input (+12V)
2 VCC
Power input (+12V)
3 VCC
Power input (+12V)
4 VCC
Power input (+12V)
5 VCC
Power input (+12V)
6 N.C.
No Connection
(2)
7 GND
Ground
8 GND
Ground
(6)
9 GND
Ground
10 ORX0-
Odd pixel Negative LVDS differential data input. Channel 0
11 ORX0+
Odd pixel Positive LVDS differential data input. Channel 0
12 ORX1-
13 ORX1+
Odd pixel Negative LVDS differential data input. Channel 1
Odd pixel Positive LVDS differential data input. Channel 1
(5)
14 ORX2-
Odd pixel Negative LVDS differential data input. Channel 2
15 ORX2+
Odd pixel Positive LVDS differential data input. Channel 2
16 GND
Ground
(6)
17 OCLK-
18 OCLK+
Odd pixel Negative LVDS differential clock input
Odd pixel Positive LVDS differential clock input
(5)
19 GND
Ground
(6)
20 ORX3-
21 ORX3+
Odd pixel Negative LVDS differential data input. Channel 3
Odd pixel Positive LVDS differential data input. Channel 3
(5)
22 N.C.
23 N.C.
No Connection
No Connection
(2)
24 GND
Ground
(6)
25 ERX0-
Even pixel Negative LVDS differential data input. Channel 0
26 ERX0+
Even pixel Positive LVDS differential data input. Channel 0
27 ERX1-
28 ERX1+
Even pixel Negative LVDS differential data input. Channel 1
Even pixel Positive LVDS differential data input. Channel 1
(5)
29 ERX2-
Even pixel Negative LVDS differential data input. Channel 2
30 ERX2+
Even pixel Positive LVDS differential data input. Channel 2
31 GND
Ground
(6)
32 ECLK-
33 ECLK+
Even pixel Negative LVDS differential clock input.
Even pixel Positive LVDS differential clock input.
(5)
Version 2.0
12 Date:8 June. 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ V400HJ3-PE1 Schematic.PDF ] |
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