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PDF V400H1-P02 Data sheet ( Hoja de datos )
| Número de pieza | V400H1-P02 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CMI MEI | |
| Logotipo |  |
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Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
TFT LCD Approval Specification
MODEL NO.: V400H1 - P02
ʳ
ʳ
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Customer:
Approved by:
Note:
Approved By
TVHD
CC Chung
Reviewed By
QA Dept.
Hsin-nan Chen
Product Development Div.
WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Josh Chi
Karen Liao
1
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Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASE ON CMO MODULE V400H1-L08)
Value
Item Symbol
Unit
Min. Max.
Note
Storage Temperature
TST -20
+60 ºC (1)
Operating Ambient Temperature
TOP
0
50 ºC (1), (2)
Shock (Non-Operating)
SNOP
-
30 G (3), (5)
Vibration (Non-Operating)
VNOP
-
1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
5
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Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
34 GND
Ground
35 ERX3-
36 ERX3+
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
(1)
37 N.C.
38 N.C.
No Connection
No Connection
(3)
39 GND
Ground
40 SCL
EEPROM Serial Clock
41 N.C.
42 N.C.
No Connection
No Connection
(3)
43 WP
EEPROM Write Protection
44 SDA
EEPROM Serial Data
45 LVDS_SEL High(3.3V) or open for VESA, Low (GND) for JEIDA
(4)
46 N.C.
No Connection
47 N.C.
No Connection
48 N.C.
49 N.C.
No Connection
No Connection
(3)
50 N.C.
No Connection
51 N.C.
No Connection
Note (1) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel
Note (2) LVDS connector pin order defined as follows
Note (3) Reserved for internal use. Please leave it open.
Note (4) Low: JEIDA LVDS Format (Connect to GND), High or open: VESA Format. (Connect to +3.3V)
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet V400H1-P02.PDF ] | |
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