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PDF L6213 Data sheet ( Hoja de datos )

Número de pieza L6213
Descripción SOLENOID DRIVER SWITCH MODE POWER SUPPLY
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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L6213
SOLENOID DRIVER + SWITCH MODE POWER SUPPLY
OPERATING SUPPLY VOLTAGE UP TO 46V
1A POWER SUPPLY (5V)
5A SOLENOID DRIVER
PRECISE ON CHIP REFERENCE VOLTAGE
DISCONTINUOUS MODE - FREQUENCY
VARIABLE
VERY HIGH EFFICIENCY
1OUTPUT DMOS (SMPS)
INTERNAL CURRENT LIMIT (SMPS SEC-
TION)
EXTERNALLY PROGRAMMABLE SOLENOID
CURRENT RISING SLOPE
EXTERNALLY PROGRAMMABLE FIXED
HYSTERESIS CONTROL
OPTIMIZED DMOS RDS ON FOR HIGH SIDE
CHOPPING
DESCRIPTION
The L6213 is an IC containing a S.M.P.S. deliver-
ing 1A at a voltage of 5V and a section designed
to drive a solenoid with a current up to 5A.
The device is realized in BCD mixed technology,
which combines isolated DMOS power transistor
with CMOS and Bipolar circuits on the same chip.
The SMPS section can deliver 1A DC with an out-
APPLICATION CIRCUIT
ADVANCE DATA
MULTIPOWER BCD TECHNOLOGY
Powerdip 16+2+2
put voltage of 5V, including current limiting, reset
and power fail for microprocessor and thermal
protection.
The solenoid driver section is designed for high
current applications like hammer driver in elec-
tronic typewriter.
The solenoid output section contains a high side and
a low side DMOS, which RDS ON are optimized for
high side chopping. The current rising slope is exter-
nally programmable through an external capacitor.
The level of hysteresis of the current can be
changed through an external resistor.
The device is supplied in Powerdip 16+2+2, and
use the four center pins to conduct heat to the
printed circuit.
November 1991
1/9
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1 page




L6213 pdf
L6213
ELECTRICAL CHARACTERISTICS (continued)
Pin Symbol
POWER FAIL
Parameter
Test Condition
Min. Typ. Max. Unit
10 VthR Rising Threshold Voltage
10 VthF Falling Threshold Voltage
10 Vth Threshold Hysteresis
8 IPFI Divided Internal Current
8 Vth-PFP Rising Threshold Voltage
8 Vth-PFP Falling Threshold Voltage
8 Vth -PFP Threshold Hysteresis
7 Vsat Output PF Saturation
7 Ileak Output Leakage Current
7 t1 Delay to Reset
7 t2 Noise Immunity
7 t3 Noise Immunity
RESET
PFP open
PFP open
PFP open
Fig. 1
Fig. 1
Fig. 1
19.5
16.6
0.5
VPS = 24V
VPS = 24V
VPS = 24V
PF current = 2.5mA
VPS = 3 to 46V
VPS = 46V VPF = 20V
RESET High to PF high
Delay Time (fig. 1)
When VPS drops to 8V for a
time from 0 to t2, PF must be
at 1 logic level (fig. 2)
When VPS drops to 17V for
a time greater than t3, PF
must be at 0 logic level (fig. 2)
1.1
0.98
30
0
0
4
20
18.1
1.21
1.06
23
19.5
130
1.29
1.13
0.4
50
1
1
V
V
V
µA
V
V
mV
V
µA
µs
µs
µs
9 Id Delay Source Current
9 Id Delay Sink Current
13 Vsat Output RESET Saturation
13 Ileak Output Leakage Current
13 t4 Noise Immunity
SOLENOID CONTROL SECTION
VD = 0 to 4.1V
VD = 4.3 to 2V
RESET Current = 2.5mA
VPS = 3 to 46V
VPS = 46V RD = 4 to 5V
VRESET = 20V
When VPS drops to 10V for a
time greater than t4 RESET
must be at 0 logic level (fig. 1)
70
10
4
140 µA
mA
0.4 V
50 µA
µs
18 Vsat Saturation Voltage
ENABLE = 1 I PIM = 5mA
0.2 V
18 Ileak Leakage Current
PIM = 0.2 to 2.5V ENABLE = 0
+100 µA
18 Vclamp Clamp Voltage
1.9 2 2.1 V
17
Minimum Offset Threshold
PIM = GND Vsens = 10mV
lower MOS must be in conduction
ENABLE = 0
17
MAximum Offset Voltage
PIM = GND Vsens = 50mV
lower MOS must be open
ENABLE = 0
17 Vsense Static Voltage Limiting
Threshold
Vsens going from 0 to 0.6V
0.475 0.5 0.525
PIM = 3V, the EMH DMOS
goes to high resistance state
when Vsens is within: (see
Block Diagram)
V
17 Maximum Delay Time
1 µs
tp Protection Time
2 4 µs
EMH Ron OnStateDrain toSource Resistance Tj = 25°C, VPS 15 to 46V
0.35 0.45
EML Ron OnStateDrain to SourceResistance Tj = 25°C, VPS 15 to 46V
0.28 0.4
17 Vsense Vsense Hysteresis
IST = Open
IST = 0.75V
IST = 3V
35 50 65 mV
15 25 35 mV
80 100 120 mV
5/9

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