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ADE7933 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADE7933
Beschreibung Isolated Energy Metering Chipset
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADE7933 Datasheet, Funktion
Data Sheet
Isolated Energy Metering Chipset
for Polyphase Shunt Meters
ADE7978/ADE7933/ADE7932
FEATURES
Enables shunt current sensors in polyphase energy meters
Immune to magnetic tampering
Highly accurate; supports EN 50470-1, EN 50470-3,
IEC 62053-21, IEC 62053-22, IEC 62053-23, ANSI C12.20,
and IEEE 1459 standards
Compatible with 3-phase, 3- or 4-wire (delta or wye) meters
and other 3-phase services
Computes active, reactive, and apparent energy on each
phase and on the overall system
Less than 0.2% error in active and reactive energy over
a dynamic range of 2000 to 1 at TA = 25°C
Less than 0.1% error in voltage rms over a dynamic range
of 500 to 1 at TA = 25°C
Less than 0.25% error in current rms over a dynamic range
of 500 to 1 at TA = 25°C
Power quality measurements including THD
Single 3.3 V supply
Operating temperature: −40°C to +85°C
Flexible I2C, SPI, and HSDC serial interfaces
Safety and regulatory approvals (pending)
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 61010-1: 400 V rms
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
Shunt-based polyphase meters
Power quality monitoring
Solar inverters
Process monitoring
Protective devices
Isolated sensor interfaces
Industrial PLCs
TYPICAL APPLICATION CIRCUIT
PHASE PHASE PHASE
NEUTRAL
A
B
C
ISOLATION
BARRIER
V1P
VM
IM PHASE A
ADE7932/
IP ADE7933
V2P
3.3V
GNDISO_A
GNDMCU
V1P
VM
IM PHASE B
ADE7932/
IP ADE7933
V2P
3.3V
GNDISO_B
GNDMCU
V1P
VM
IM PHASE C
ADE7932/
IP ADE7933
V2P
3.3V
ADE7978
ENERGY
METERING
IC
3.3V
I2C/HSDC OR SPI
IRQ0, IRQ1
GNDMCU
3.3V
GNDMCU
LOAD
GNDISO_C
GNDMCU
V1P
VM NEUTRAL
IM
LINE
ADE7932/
ADE7933
IP (OPTIONAL)
V2P
3.3V
GNDISO_N
GNDMCU
EARTH
Figure 1. 3-Phase, 4-Wire Meter with Four ADE7933/ADE7932 Devices and One ADE7978
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; and 7,558,080. Other patents are pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADE7933 Datasheet, Funktion
ADE7978/ADE7933/ADE7932
VDDISO
GNDISO
1
2
LDO 8
3
V2P
5
VM
V1P
IM
IP
REF
4
6
7
9
10
GNDISO
ISOLATION
BARRIER
ADE7933
LDO
TEMP
SENSOR
ADC
ADC
ADC
VREF
POWER
ISOLATION
DATA
CLOCK
DATA
ISOLATION
DATA
CLOCK
DIGITAL
BLOCK
AND
ADE7978
INTERFACE
Figure 3. ADE7933 Functional Block Diagram
19 VDD
20 GND
18 EMI_CTRL
17 V2/TEMP
16 RESET_EN
15 DATA
14 XTAL2
13 XTAL1
12 SYNC
11 GND
VDDISO
GNDISO
1
2
LDO 8
3
V2P
5
VM
V1P
IM
IP
REF
4
6
7
9
10
GNDISO
ISOLATION
BARRIER
ADE7932
LDO
TEMP
SENSOR
POWER
ISOLATION
ADC
ADC
ADC
DATA
CLOCK
DATA
ISOLATION
DATA
CLOCK
DIGITAL
BLOCK
AND
ADE7978
INTERFACE
VREF
Figure 4. ADE7932 Functional Block Diagram
19 VDD
20 GND
18 EMI_CTRL
17 V2/TEMP
16 RESET_EN
15 DATA
14 XTAL2
13 XTAL1
12 SYNC
11 GND
Data Sheet
Rev. 0 | Page 6 of 120

6 Page









ADE7933 pdf, datenblatt
ADE7978/ADE7933/ADE7932
HSDC Interface Timing Parameters
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C.
Table 5.
Parameter
HSA to HSCLK Edge
HSCLK Period
HSCLK Low Pulse Width
HSCLK High Pulse Width
Data Output Valid After HSCLK Edge
Data Output Fall Time
Data Output Rise Time
HSCLK Rise Time
HSCLK Fall Time
HSD Disable After HSA Rising Edge
HSA High After HSCLK Edge
Symbol
tSS
tSL
tSH
tDAV
tDF
tDR
tSR
tSF
tDIS
tSFS
Min
0
125
50
50
5
0
Max Unit
ns
ns
ns
ns
40 ns
20 ns
20 ns
10 ns
10 ns
ns
ns
HSA
tSS
tSFS
HSCLK
tDAV
tSL
tSH
tSF tSR
tDIS
HSD
MSB
INTERMEDIATE BITS
LSB
tDF
Figure 7. HSDC Interface Timing
tDR
2mA
IOL
TO OUTPUT
PIN CL
50pF
800µA
IOH
1.6V
Figure 8. Load Circuit for Timing Specifications
Data Sheet
Rev. 0 | Page 12 of 120

12 Page





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