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25LV010 Schematic ( PDF Datasheet ) - ELAN Microelectronics

Teilenummer 25LV010
Beschreibung EM25LV010
Hersteller ELAN Microelectronics
Logo ELAN Microelectronics Logo 




Gesamt 30 Seiten
25LV010 Datasheet, Funktion
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
General Description
The EM25LV010 is a 1 M bits Flash memory organized as 128K x 8 bits and uses a single
voltage of 2.7-3.6V for Program and Erase. It features a typical 2ms Page-Program time and
a typical 40ms Block-Erase time. The device uses status register to detect the completion of
the Program or Erase operation. To protect against inadvertent write, the device has on-chip
hardware and software data protection schemes. The device offers typical 100,000 cycles
endurance and a greater than 10 years data retention. The EM25LV010 conforms to SPI
Bus compatible Serial Interface. It consisted of four pins (serial clock, chip select, serial data
in, and serial data out) that support high-speed serial data transfers of up to 33MHz. The
Hold pin, Write Protect pin, and Programmable Write Protect features provide flexible control.
The EM25LV010 is offered in 8-lead SO package and known good die (KGD). For KGD,
please contact ELAN Microelectronics or its representatives for detailed information (see
Appendix at the bottom of this specification for Ordering Information).
The EM25LV010 devices are suitable for applications that require memories with convenient
and economical updating of program, data or configurations, e.g., graphic cards, hard disk
drives, networking cards, digital camera printer, LCD monitors, cordless Phones, etc.
Features
Single Power Supply
Full voltage range from 2.7 to 3.6
volts for both read and write operations
Regulated voltage range: 3.0 to 3.6
volts for both read and write operations
Small block Erase Capability
Block: Uniform 32K bytes
Clock Rate
33MHz (Maximum)
Power Consumption
Active Current: 4mA (Typical)
Power-down Mode Standby
current: 1µA (Typical)
Page Program Features
Up to 256 Bytes in 2ms (Typical)
Erase Features
Block-Erase Time: 40ms (Typical)
Chip-Erase Time: 40ms (Typical)
Automatic Write Timing
Internal VPP Generation
SPI Bus Compatible Serial Interface
High Reliability:
Endurance cycles: 100K (Typical)
Data retention: 10 years
Package Option
8-lead-SO (150 mil)
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 1 of 30






25LV010 Datasheet, Funktion
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Status Register
The Status Register contains a number of status and control bits that can be read or set by
specific instructions. Refer to Table 3 below for details.
BUSY Bit
The (BUSY) bit is a read only bit in the status register, which is set to “1” state when the device
is executing the Write Status Register, Program, or Erase cycle while the device ignores
further instructions except for the Read Status Register instruction. When the Program,
Erase, or Write Status Register instruction is completed, the (BUSY) bit will be cleared to “0”
state indicating the device is ready for further instructions.
WEL Bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When setting to “1,” the internal Write Enable Latch is set. When setting to “0,” the internal
Write Enable Latch is reset and no Write Status Register, Program, nor Erase instruction is
accepted.
BP1, BP0 Bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0)
bits is set to “1”, the relevant memory area, as defined in Table 4, becomes protected against
Page Program (PP) and Block Erase (BE) instructions. The Block Protect (BP1, BP0) bits can
be written provided that the Hardware Protected mode has not been set. The Chip Erase
(CE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are set to “0.”
SRWD Bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W#) signal. The Status Register Write Disable bit and Write Protect signal allow the
device to be located in the Hardware Protected mode (when the Status Register Write Disable
(SRWD) bit is set to “1,” and Write Protect (W#) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, and BP0) become read-only bits and the Write Status
Register (WRSR) instruction is no longer accepted for execution.
This specification is subject to change without further notice. (11.08.2004 V1.0)
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25LV010 pdf, datenblatt
EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 10) sets the Write Enable Latch (WEL) bit to “1”.
The Write Enable Latch (WEL) bit must be set prior to the Page Program (PP), Block Erase
(BE), Chip Erase (CE), and Write Status Register (WRSR) instructions. The Write Enable
(WREN) instruction is entered by driving Chip Select (S#) Low, sending the instruction code,
and then driving Chip Select (S#) High.
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 11) resets the Write Enable Latch (WEL) bit to
“0.” The Write Disable (WRDI) instruction is entered by driving Chip Select (S#) Low,
sending the instruction code, and then driving the Chip Select (S#) High. The Write Enable
Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completed
Write Status Register (WRSR) instruction completed
Page Program (PP) instruction completed
Block Erase (BE) instruction completed
Chip Erase (CE) instruction completed
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the 8-bit Status Register to be read.
The Status Register may be read any time, even while a Program, Erase, or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the (BUSY) bit before sending a new instruction to the device. It is also allowed to read
the Status Register continuously, as shown in Figure 12.
An improvement in the time to Write Status Register (WRSR), Program (PP), or Erase (SE,
BE or CE) can be achieved by not waiting for the worst-case delay (tW, tPP, tSE, tBE or tCE).
The (BUSY) bit is provided in the Status Register so that the system application program can
monitor its value, polling it to “0” when the previous Write cycle, Program cycle, or Erase cycle
is completed.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it is accepted, a Write Enable (WREN) instruction must be executed first.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets
the Write Enable Latch (WEL).
This specification is subject to change without further notice. (11.08.2004 V1.0)
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