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PDF MK2302-01 Data sheet ( Hoja de datos )
| Número de pieza | MK2302-01 | |
| Descripción | MULTIPLIER AND ZERO DELAY BUFFER | |
| Fabricantes | IDT | |
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MULTIPLIER AND ZERO DELAY BUFFER
DATASHEET
MK2302-01
Description
The MK2302-01 is a high performance Zero Delay Buffer
(ZDB) which integrates IDT’s proprietary analog/digital
Phase Locked Loop (PLL) techniques. The chip is part of
IDT’s ClockBlocksTM family and was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature means
that the rising edge of the input clock aligns with the rising
edges of both output clocks, giving the appearance of no
delay through the device. There are two outputs on the chip,
one being a low-skew divide by two of the other output.
The MK2302-01 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
Features
• 8-pin SOIC package
• Pb (lead) free package
• Low input to output skew of 250 ps max
• Absolute jitter ± 500 ps
• Propagation Delay ± 350 ps
• Ability to choose between different multipliers from 0.5X
to 16X
• Output clock frequency up to 168 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Full CMOS clock swings with 25mA drive capability at
TTL levels
• Advanced, low power CMOS process
• Operating voltage of 3.3 V or 5 V
• Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
divide
by N
Phase
D e te cto r,
C ha rg e
Pump,
and Loop
F ilte r
VCO
/2
CLK1
CLK2
External feedback can com e from C LK1 or C LK2 (see table on page 2)
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
1
MK2302-01 REV G 051310
1 page  
MK2302-01
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
AC Electrical Characteristics
VDD = 3.3 V or 5 V ±5%, Ambient Temperature 0 to +70° C or -40° C to 85° C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency, ICLK
FBIN from CLK/2
See table on page 2
Output Clock Frequency
CLK1
10 168 MHz
Output to Output Skew
100 175 ps
Input to Output Jitter
40 - 150 MHz
200 ps
Input Skew
ICLK to FBIN,
-300
CLK>30 MHz, Note 1
300 ps
ICLK to FBIN,
-600
CLK<30 MHz, Note 1
600 ps
Output Clock Rise Time
0.8 to 2.0 V, Note 2
0.8 1 ns
Output Clock Fall Time
2.0 to 0.8 V, Note 2
0.8 1 ns
Output Clock Duty Cycle
at VDD/2
40 49 - 51 60
%
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Note 2: Measured with 27Ω terminating resistor and 15 pF loads.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
150
140
120
40
Max.
Units
° C/W
° C/W
° C/W
° C/W
IDT™ MULTIPLIER AND ZERO DELAY BUFFER
5
MK2302-01 REV G 051310
5 Page | ||
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| PDF Descargar | [ Datasheet MK2302-01.PDF ] | |
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