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PDF MC96P6608 Data sheet ( Hoja de datos )
| Número de pieza | MC96P6608 | |
| Descripción | 8-BIT MICROCONTROLLERS | |
| Fabricantes | ABOV | |
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MC96P6608/P6408
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC96P6608/P6408
User’s Manual (Ver. 1.4)
April 21, 2015 Ver. 1.4
1
1 page  
MC96P6608/P6408
Figure 1.2 PGMplusUSB (Single Writer)................................................................................................. 13
Figure 1.3 StandAlone PGMplus (Single Writer)..................................................................................... 13
Figure 1.4 StandAlone Gang8 (for Mass Production) ............................................................................. 13
Figure 1.5 PCB Design Guide for On Board Programming..................................................................... 15
Figure 2.1 Block Diagram ....................................................................................................................... 16
Figure 3.1 MC96P6608 64LQFP-1010 Pin Assignment ......................................................................... 17
Figure 3.2 MC96P6408 48LQFP-0707 Pin Assignment ......................................................................... 18
Figure 4.1 64-Pin LQFP Package ........................................................................................................... 19
Figure 4.2 48-Pin LQFP Package ........................................................................................................... 20
Figure 6.1 General Purpose I/O Port ...................................................................................................... 24
Figure 6.2 External Interrupt I/O Port ...................................................................................................... 25
Figure 7.1 Input Timing for External Interrupts........................................................................................ 31
Figure 7.2 Input Timing for RESETB ...................................................................................................... 31
Figure 7.3 Serial Interface Data Transfer Timing .................................................................................... 32
Figure 7.4 Stop Mode Release Timing when Initiated by an Interrupt .................................................... 33
Figure 7.5 Stop Mode Release Timing when Initiated by RESETB ........................................................ 33
Figure 7.6 Crystal/Ceramic Oscillator ..................................................................................................... 35
Figure 7.7 External Clock........................................................................................................................ 35
Figure 7.8 Crystal Oscillator.................................................................................................................... 36
Figure 7.9 External Clock........................................................................................................................ 36
Figure 7.10 Clock Timing Measurement at XIN ...................................................................................... 37
Figure 7.11 Clock Timing Measurement at SXIN .................................................................................... 37
Figure 7.12 Operating Voltage Range .................................................................................................... 38
Figure 7.13 Recommended Circuit and Layout....................................................................................... 39
Figure 7.14 RUN (IDD1) Current ............................................................................................................ 40
Figure 7.15 IDLE (IDD2) Current ............................................................................................................ 40
Figure 7.16 SUB RUN (IDD3) Current .................................................................................................... 41
Figure 7.17 SUB IDLE (IDD4) Current .................................................................................................... 41
Figure 7.18 STOP (IDD5) Current .......................................................................................................... 42
Figure 8.1 Program Memory ................................................................................................................... 44
Figure 8.2 Data Memory Map ................................................................................................................. 45
Figure 8.3 Lower 128 Bytes RAM ........................................................................................................... 46
Figure 10.1 External Interrupt Description .............................................................................................. 79
Figure 10.2 Block Diagram of Interrupt ................................................................................................... 80
Figure 10.3 Interrupt Vector Address Table ............................................................................................ 82
Figure 10.4 Effective Timing of Interrupt Enable Register...................................................................... 83
Figure 10.5 Effective Timing of Interrupt Flag Register........................................................................... 83
Figure 10.6 Effective Timing of Interrupt ................................................................................................. 84
Figure 10.7 Interrupt Response Timing Diagram .................................................................................... 85
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP ................. 85
Figure 10.9 Saving/Restore Process Diagram and Sample Source ....................................................... 85
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction .............................. 86
Figure 11.1 Clock Generator Block Diagram .......................................................................................... 92
Figure 11.2 PLL Circuit Diagram............................................................................................................. 93
Figure 11.3 Basic Interval Timer Block Diagram ..................................................................................... 96
Figure 11.4 Watch Dog Timer Interrupt Timing Waveform...................................................................... 98
Figure 11.5 Watch Dog Timer Block Diagram......................................................................................... 99
Figure 11.6 Watch Timer Block Diagram .............................................................................................. 101
April 21, 2015 Ver. 1.4
5
5 Page 
1.3 Ordering Information
Table 1-1 Ordering Information of MC96P6608/P6408
Device name
MC96P6608L
MC96P6408L
ROM size
8k bytes OTP
8k bytes OTP
MC96P6608/P6408
IRAM size
256 bytes
256 bytes
Package
64 LQFP
48 LQFP
April 21, 2015 Ver. 1.4
11
11 Page | ||
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| PDF Descargar | [ Datasheet MC96P6608.PDF ] | |
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