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T500HVD02.0 Schematic ( PDF Datasheet ) - AUO

Teilenummer T500HVD02.0
Beschreibung TFT LCD MODULE
Hersteller AUO
Logo AUO Logo 




Gesamt 28 Seiten
T500HVD02.0 Datasheet, Funktion
T500HVD02.0 SKD Product Specification
Rev.0 0
Model Name: T500HVD02.0
Issue Date: 2012/07/24
()Preliminary Specifications
( )Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
CP Wang
____________________________________
Note
Reviewed By RD Director
Eugene Chen
____________________________________
Reviewed By Project Leader
Solon Hung
____________________________________
Prepared By PM
ChihYang Wang
____________________________________
© Copyright AUO Optronics Corp. 2012 All Rights Reserved.
Page 1 / 28






T500HVD02.0 Datasheet, Funktion
3. Electrical Specification
T500HVD02.0 SKD Product Specification
Rev.0 0
The T500HVD02.0 Open Cell Unit requires power input which is employed to power the LCD electronics and to
drive the TFT array and liquid crystal.
3.1 Electrical Characteristics
3.1.1: DC Characteristics
Parameter
LCD
Power Supply Input Voltage
Power Supply Input Current
Power Consumption
Inrush Current
Permissible Ripple of Power Supply Input Voltage
Input Differential Voltage
LVDS Differential Input High Threshold Voltage
Interface Differential Input Low Threshold Voltage
Input Common Mode Voltage
CMOS Input High Threshold Voltage
Interface Input Low Threshold Voltage
Symbol
VDD
IDD
PC
IRUSH
VRP
∣ ∣VID
VTH
VTL
VICM
VIH
(High)
VIL
(Low)
Min.
10.8
--
--
--
--
200
+100
-300
1.1
2.7
0
Value
Typ.
Max
Unit Note
12
1.03
12.36
--
--
400
13.2
1.24
16.4
4
VDD * 5%
600
VDC
A
Watt
A
mVpk-pk
mVDC
--
+300
mVDC
--
1.25
-100
1.4
mVDC
VDC
-- 3.3 VDC
-- 0.6 VDC
1
1
2
3
4
4
4
4
5
5
3.1.2: AC Characteristics
Parameter
LVDS
Interface
Receiver Clock : Spread Spectrum
Modulation range
Receiver Clock : Spread Spectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
Fclk = 65 MHz
Symbol
Fclk_ss
Fss
Min.
Fclk
-3%
30
Value
Typ.
--
--
Max
Fclk
+3%
200
Unit Note
MHz
KHz
6
6
tRMG
-0.4
--
0.4
ns 7
-0.5 --
0.5
© Copyright AUO Optronics Corp. 2012 All Rights Reserved.
Page 6 / 28

6 Page









T500HVD02.0 pdf, datenblatt
3.3 Signal Timing Specification
T500HVD02.0 SKD Product Specification
Rev.0 0
This is the signal timing required at the input of the user connector. All of the interface signal timing should be
satisfied with the following specifications for its proper operation.
Timing Table (DE only Mode)
Signal
Item
Period
Vertical Section
Active
Blanking
Period
Horizontal Section
Active
Blanking
Clock
Frequency
Vertical Frequency
Frequency
Horizontal Frequency Frequency
Symbol
Tv
Tdisp (v)
Tblk (v)
Th
Tdisp (h)
Tblk (h)
Fclk=1/Tclk
Fv
Fh
Min.
1100
20
1030
70
50
47
60
Typ.
1125
1080
45
1100
960
140
74.25
60
67.5
Max
1480
Unit
Th
400
1325
Th
Tclk
365 Tclk
82 MHz
63 Hz
73 KHz
Notes:
(1) Display position is specific by the rise of DE signal only.
Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the
left edge of the screen.
(2)Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of
horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top
line of screen.
(3)If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.
(4)The display position does not fit to the screen if a period of DE “High” and the effective data period do not
synchronize with each other.
(5) Under 3D mode, signal should be input as following sequence: 1st line: right eye, 2nd line: left eye (when rotate
function is not implemented and Tcon position is at panel upper side).
© Copyright AUO Optronics Corp. 2012 All Rights Reserved.
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