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25Q16BSIG Schematic ( PDF Datasheet ) - GigaDevice

Teilenummer 25Q16BSIG
Beschreibung Uniform Sector Dual and Quad Serial Flash
Hersteller GigaDevice
Logo GigaDevice Logo 




Gesamt 30 Seiten
25Q16BSIG Datasheet, Funktion
25Q16BSIG
FEATURES
16M-bit Serial Flash
-2048K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 180Mbits/s
-Quad I/O Data transfer up to 360Mbits/s
Program/Erase Speed
-Page Program time: 0.7ms typical
-Sector Erase time: 100ms typical
-Block Erase time: 0.3/0.4/0.8s typical
-Chip Erase time: 16s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64/128K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
-Write protect all/portion of memory via software
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
Minimum 100,000 Program/Erase Cycles
Note: 1.Please contact Gigadevice for details.
Advanced security Features(1)
-16-Bit Customer ID
-Security Architecture
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
GENERAL DESCRIPTION
The GD25Q16 (16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O
data is transferred with speed of 180Mbits/s and the Quad I/O & Quad output data is transferred with speed of
360Mbits/s.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1






25Q16BSIG Datasheet, Funktion
Uniform Sector
Dual and Quad Serial Flash
GD25Q16
Status Register
S15-S10
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Reserved
QE SRP1 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.
When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in
Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block
Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP2, BP1, BP0) bits are 0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1 SRP0 #WP
Status Register
Description
00X
Software Protected
The Status Register can be written to after a Write Enable
command, WEL=1.(Default)
010
Hardware Protected
WP#=0, the Status Register locked and can not be written to.
011
Hardware Unprotected
WP#=1, the Status Register is unlocked and can be written to
after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
1 0 X Power Supply Lock-Down(1)
until the next Power-Down, Power-Up cycle.
11X
One Time Program
Status Register is permanently protected and can not be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
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25Q16BSIG pdf, datenblatt
Uniform Sector
Dual and Quad Serial Flash
GD25Q16
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
and IO0. The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure9. Quad Output Fast Read Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Command
6BH
24-bit address
23 22 21
3210
High-Z
High-Z
High-Z
CS#
SCLK
SI(IO0)
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
40404040 4
SO(IO1)
515151515
WP#(IO2)
626262626
HOLD#(IO3)
737373737
Byte1 Byte2 Byte3 Byte4
Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a Continuous Read Modebyte 2-bit per clock by SI and SO, each bit being latched in
during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The
command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum
performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read
command.
Dual I/O Fast Read With Continuous Read Mode
The Dual I/O Fast Read command can further reduce command overhead through setting the Continuous Read
Modebits (M7-0) after the input 3-byte address (A23-A0). If the Continuous Read Modebits (M7-0) =AXH, then the next
Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The
command sequence is shown in followed Figure11. If the Continuous Read Modebits (M7-0) are any value other than
AXH, the next command requires the first BBH command code, thus returning to normal operation. A Continuous Read
ModeReset command can be used to reset (M7-0) before issuing normal command.
12

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