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AR2317 Schematic ( PDF Datasheet ) - Atheros

Teilenummer AR2317
Beschreibung Single Chip MAC/Baseband/Radio and Processor
Hersteller Atheros
Logo Atheros Logo 




Gesamt 30 Seiten
AR2317 Datasheet, Funktion
Data Sheet
PRELIMINARY
April 2006
AR2317 Single Chip MAC/Baseband/Radio and Processor
for 2.4 GHz Wireless LANs
General Description
Features
The Atheros AR2317 is an all-CMOS, fully-
Integrated high-output PA
integrated, single-chip 802.11b/g WLAN
Integrated LNA/optional external LNA
solution. It integrates the PA, LNA, 2.4GHz
support
radio, baseband PHY, MAC, and a MIPS 4000
Integrated 1.8 V voltage regulator; NO need
CPU into a single chip for wireless access point
for a 1.8 V supply
and router applications. Other major modules
Switched Rx antenna diversity
include 802.3 Ethernet MAC and MII interface,
Integrated Rx/Tx antenna switch
SDRAM controller, external memory interface
Integrated power detector
for Flash, ROM, or RAM, a UART, GPIOs as
25 MHz output for Ethernet switch
well as LED controls.
The AR2317 implements an 802.11 MAC/BB
processor supporting all IEEE 802.11g data
rates (1 to 54 Mbps) and all IEEE 802.11b
Ycomplementary key coding (CCK) data rates
(1 to 11 Mbps). Additional features include
Pforward error correction coding at rates for 1/
2, 2/3, and 3/4, signal detection, automatic
Ogain control, frequency offset estimation,
symbol timing, channel estimation, error
Crecovery, enhanced security, and quality of
service (QoS). The AR2317 performs receive
Tand transmit filtering for IEEE 802.3 and 802.11
networks.
DO NOSystem Block Diagram
Integrated MIPS 4000 processor
180 MHz processor frequency
IEEE 802.11b/g Access Point, Ad Hoc, and
station functions supported
OFDM and CCK modulation schemes
supported
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, 54 Mbps
IEEE 802.3 Ethernet MAC supporting 10/
100 Mbps, full and half duplex, and MII
interface to external Ethernet PHY
UART for console support
IEEE 1149.1 standard test access port and
boundary scan architecture supported
EJTAG based debugging of the processor
core supported
Standard 0.18 μm CMOS technology
12 mm x 12 mm 260 BGA package
Flash SDRAM Interface
LNA
LNA
RF
Switch
PA
AR2317
Receiver
Frequency
Synthesizer
Transmitter
Bias/
Control
SDRAM
Controller
and Memory
Interface
MIPS
Processor
Baseband
(PHY) and
Wireless MAC
Ethernet
MAC
Fast UART
Peripheral
Interface
MII Interface
40 MHz
Crystal
Serial Interface
LED Controls
GPIOs
© 2000-2006 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
1






AR2317 Datasheet, Funktion
Table 1-1. AR2317 Pin Assignments (1–11)
123
GND
A
GND
VDD18_
BYPASS
B GND
GND
GND
C VDD33
GND
NA
D SD_DATA_12 SD_DATA_2
NA
E SD_DATA_11 SD_DATA_3
NA
F SD_DATA_5 SD_DATA_4
NA
G SD_DATA_6 SD_DATA_10
NA
H SD_DATA_7 SD_DATA_9
NA
J
VDD33
SD_DATA_8
NA
K VDD33
VDD33
NA
L VDD33
VDD33
NA
VDD18_
VDD18_
M BYPASS
BYPASS
NA
VDD18_
VDD18_
N BYPASS
BYPASS
NA
P SD_DQM_0 DLDO_PWD
NA
R DLDO_SEL1 SD_WE_L
NA
T DLDO_SEL0 SD_DQM_1
NA
U SD_CAS_L SD_CLK_FB
NA
V SD_CKE SD_CLK
NA
W SD_RAS_L SD_ADDR_12
NA
VDD18_
Y BYPASS
GND
NA
AA GND
GND
GND
AB GND
GND
VDD33
45
SD_DATA_14 SD_DATA_15
SD_DATA_1
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
SD_DATA_13
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
SD_ADDR_11 SD_ADDR_9
SD_CS_L SD_BANK_1
6
GPIO_2
7
GPIO_7
8
GPIO_5
9
GPIO_3
10
NC
SD_DATA_0 PROC_REF_CLK
NA NA
NA NA
NA NA
NA NA
NA GND
NA GND
NA GND
NA GND
NA GND
NA GND
GPIO_4
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GPIO_1
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GPIO_0
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
NA
GND
GND
GND
GND
NA
GND
GND
GND
GND
NA
GND
GND
GND
GND
NA
GND
GND
GND
GND
NA
NA
NA NA
NA
NA
NA
NA NA
NA
NA
NA
NA NA
NA
NA
NA
NA NA
NA
SD_ADDR_8 SD_ADDR_7 SD_ADDR_6 SD_ADDR_5 SD_ADDR_4
SD_BANK_0 SD_ADDR_10 SD_ADDR_0 SD_ADDR_1 SD_ADDR_2
11
AVDD33
AVDD33
NA
NA
NA
NA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NA
NA
NA
NA
CLK_25
SD_ADDR_3

6 Page









AR2317 pdf, datenblatt
PRELIMINARY
2.2.1 Radio Receiver Characteristics
Table 2-4 summarizes the receiver
characteristics for the AR2317.
Table 2-4. Receiver Characteristics for Antenna 2 (Primary Receiver)
Symbol Parameter
Conditions
Min
Typ Max
Frx Receive input frequency range
5 MHz center
frequency
2.312
— 2.484
NF Receive chain noise figure
— — 6—
Srf Sensitivity
See Note [1]
CCK, 1 Mbps
CCK, 11 Mbps
OFDM, 6 Mbps
OFDM, 54 Mbps
— –96 —
— –88 —
— –91 —
— –74 —
IP1dB Input 1 dB compression (min. gain)
— –10 —
IIP3 Input third intercept point
— — –1
(min. gain)
ZRFin_input Recommended LNA differential
drive impedance
ERphase I,Q phase error
YERamp I,Q amplitude error
PRadj
Adjacent channel rejection
OCCK
OFDM, 6 Mbps
COFDM, 54 Mbps
TRpowup Time for power up (from synth on)
See Note [2]
10 to 20 MHz [3]
T[1]Performance is based on the Atheros reference design.
[2]Refer to the Hardware Design Guide for information.
DO NO[3]Measured with AR2317.
35
16
–1
TBD
1
0.9
40
20
1
Unit
GHz
dB
dBm
dBm
dBm
degree
dB
dB
μs
12 • AR2317 MAC/BB/Radio and Processor for 2.4 GHz WLANs
12 April 2006
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

12 Page





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