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P550HVN04.0 Schematic ( PDF Datasheet ) - AUO

Teilenummer P550HVN04.0
Beschreibung TFT LCD Module
Hersteller AUO
Logo AUO Logo 




Gesamt 30 Seiten
P550HVN04.0 Datasheet, Funktion
Global LCD Panel Exchange Center
www.panelook.com
P550HVN04.0 Product Specification
Rev0.0
Model Name: P550HVN04.0
Issue Date : 2013/08/02
(Ϡ) Preliminary Specifications
()Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
Kelly Kao
_____________________________
Note
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
MingYu Wu
____________________________________
Prepared By PM
Travis Huang
____________________________________
© Copyright AU Optronics Corp. 2013 All Rights Reserved.
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P550HVN04.0 Datasheet, Funktion
Global LCD Panel Exchange Center
www.panelook.com
3. Electrical Specification
P550HVN04.0 Product Specification
Rev0.0
The P550HVN04.0 requires three power inputs. Two of them are employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The third is employed for LED driver. P550HVN04.0 contains two LVDS input,
which are applied to two sides. The LVDS connector for side A only can be seen via the front of side A, and the
LVDS connector for side B only can be seen via side B.
3.1.1 Electrical Characteristics
Parameter
Value
Symbol
Unit Note
Min. Typ.
Max
LCD
Power Supply Input Voltage
VDD 10.8
12
13.2
VDC
Power Supply Input Current
IDD -- 0.48 1.1
A
1
Power Consumption
Inrush Current
Permissible Ripple of Power Supply Input
Voltage
(for input power=12V)
Input Differential Voltage
Differential Input High Threshold
LVDS
Voltage
PC
IRUSH
VRP
Ю ЮVID
VTH
--
-
--
200
+100
5.76 13.2
4
Watt
A
--
VDD * 5%
mVpk-pk
400 600 mVDC
--
+300
mVDC
1
2
3
4
4
Interface Differential Input Low Threshold
VTL -300
Voltage
--
-100
mVDC
4
Input Common Mode Voltage
VICM 1.1 1.25
1.4
VDC
4
CMOS
Interface
Input High Threshold Voltage
Input Low Threshold Voltage
VIH
(High)
VIL
(Low)
2.7
0
--
--
3.3 VDC
0.6 VDC
7
Backlight Power Consumption
PBL
-- 183.12 189.36
W
Life Time(MTTF)
3.1.2 AC Characteristics
Parameter
LVDS
Interface
Receiver Clock : Spread
Spectrum
Modulation range
Receiver Clock : Spread
ʳSpectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
50000 60000
Value
Symbol
Min. Typ. Max
Fclk Fclk
Fclk_ss
--
-3% +3%
ʳ ʳ ʳ ʳFss 30 -- 200
ʳ ʳtRMG
-0.4
--
0.4
--
Unit
MHz
ʳKHz
ʳns
8
Note
9
9
10
© Copyright AU Optronics Corp. 2013 All Rights Reserved.
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P550HVN04.0 pdf, datenblatt
Global LCD Panel Exchange Center
www.panelook.com
3.3 Signal Timing Specification
P550HVN04.0 Product Specification
Rev0.0
This is the signal timing required at the input of the user connector. All of the interface signal timing should be
satisfied with the following specifications for its proper operation.
Timing Table (DE only Mode)
Vertical Frequency Range (60Hz)
Signal
Item
Symbol
Min. Typ. Max Unit
Period
Tv
1100
1125
1480
Th
Vertical Section
Active
Tdisp (v)
1080
Th
Blanking
Tblk (v)
20 45 400 Th
Period
Th
1040
1100
1328
Tclk
Horizontal Section
Active
Tdisp (h)
960 Tclk
Blanking
Tblk (h)
80 140 368 Tclk
Clock
Frequency
Fclk=1/Tclk
53
74.25
82 MHz
Vertical Frequency
Frequency
Fv
47 60 63 Hz
Horizontal Frequency Frequency
Fh
60 67.5 73 KHz
Notes:
(1) Display position is specific by the rise of DE signal only.
Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the
left edge of the screen.
(2)Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of
horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top
line of screen.
(3)If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.
(4)The display position does not fit to the screen if a period of DE “High” and the effective data period do not
synchronize with each other.
© Copyright AU Optronics Corp. 2013 All Rights Reserved.
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