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PDF UDA1361TS Data sheet ( Hoja de datos )
| Número de pieza | UDA1361TS | |
| Descripción | 96 kHz sampling 24-bit stereo audio ADC | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
UDA1361TS
96 kHz sampling 24-bit stereo audio
ADC
Product specification
Supersedes data of 2001 Jan 17
2002 Nov 25
1 page  
NXP Semiconductors
96 kHz sampling 24-bit stereo audio ADC
Product specification
UDA1361TS
FUNCTIONAL DESCRIPTION
System clock
The UDA1361TS accommodates master and slave
modes. The system devices must provide the system clock
regardless of master or slave mode. In the master mode a
system clock frequency of 256fs is required. In the slave
mode a system frequency of 256, 384, 512 or 768fs is
automatically detected (for a system clock of 768fs the
sampling frequency must be limited to 55 kHz). The
system clock must be locked in frequency to the digital
interface input signals.
Input level
The overall system gain is proportional to VDDA, or more
accurately the potential difference between the reference
voltages VVRP and VVRN. The −1 dB input level at which
THD + N/S is specified corresponds to −1 dB(FS) digital
output (relative to the full-scale swing). With an input gain
switch, the input level can be calculated as follows:
at 0 dB gain:
Vi(–1 dB)
=
-V----V---R----P----–-----V----V---R----N--
3
=
V (RMS)
at 6 dB gain:
Vi(–1 dB)
=
-V----V---R----P----–-----V----V---R----N--
2×3
=
V (RMS)
In applications where a 2 V (RMS) input signal is used, a
12 kΩ resistor must be connected in series with the input
of the ADC. This forms a voltage divider together with the
internal ADC resistor and ensures that only 1 V (RMS)
maximum is input to the IC.
Using this application for a 2 V (RMS) input signal, the gain
switch must be set to 0 dB. When a 1 V (RMS) input signal
is input to the ADC in the same application the gain switch
must be set to 6 dB.
An overview of the maximum input voltage allowed against
the presence of an external resistor and the setting of the
gain switch is given in Table 1. The power supply voltage
is assumed to be 3 V.
Table 1 Application modes using input gain stage
RESISTOR
(12 kΩ)
Present
Present
Absent
Absent
INPUT GAIN
SWITCH
0 dB
0 dB
0 dB
6 dB
MAXIMUM
INPUT
VOLTAGE
(RMS)
2V
1V
1V
0.5 V
Multiple format output interface
The serial interface provides the following data output
formats in both master and slave modes
(see Figs 3, 4 and 5):
• I2S-bus with data word length of up to 24 bits
• MSB-justified serial format with data word length of up to
24 bits.
The master mode drives pins WS (word select; 1fs) and
BCK (bit clock; 64fs). WS and BCK are received in slave
mode.
Table 2 Master/slave select
MSSEL
L
H
M
MASTER/SLAVE
SELECT
slave mode
master mode
(reserved for digital test)
Table 3 Select data format
SFOR
L
H
M
DATA FORMAT
I2S-bus data format
MSB-justified data format
(reserved for analog test)
Decimation filter
The decimation from 64fs is performed in two stages. The
first stage realizes a 4th-order sinx/x characteristic. This
filter decreases the sample rate by 8.
The second stage, a FIR filter, consists of 3 half-band
filters, each decimating by a factor of 2.
2002 Nov 25
5
5 Page 
NXP Semiconductors
96 kHz sampling 24-bit stereo audio ADC
Product specification
UDA1361TS
handbook, full pagewidth
WS
BCK
DATAO
tr tBCKH tf
t BCKL
Tcy(CLK)(bit)
t d(WS)(BCK)
t h(o)(D)
t d(o)(D)(BCK)
MGT454
Fig.4 Serial interface master mode timing.
handbook, full pagewidth
WS
BCK
DATAO
tr tBCKH tf
t h(WS)
t su(WS)
t BCKL
Tcy(CLK)(bit)
t d(o)(D)(WS)
t h(o)(D)
t d(o)(D)(BCK)
MGT455
2002 Nov 25
Fig.5 Serial interface slave mode timing.
11
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| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet UDA1361TS.PDF ] | |
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