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PDF DM74S182 Data sheet ( Hoja de datos )
| Número de pieza | DM74S182 | |
| Descripción | Look-Ahead Carry Generator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1986
Revised March 2000
DM74S182
Look-Ahead Carry Generator
General Description
These circuits are high-speed, look-ahead carry genera-
tors, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to per-
form full look-ahead across n-bit adders. Carry, generate-
carry, and propagate-carry functions are provided as
shown in the pin designation table.
When used in conjunction with the 181 arithmetic logic unit,
these generators provide high-speed carry look-ahead
capability for any word length. Each DM74S182 generates
the look-ahead (anticipated carry) across a group of four
ALU’s and, in addition, other carry look-ahead circuits may
be employed to anticipate carry across sections of four
look-ahead packages up to n-bits. The method of cascad-
ing circuits to perform multi-level look-ahead is illustrated
under typical application data.
Carry input and output of the ALU’s are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, out-
puts, generate, and propagate) of the look-ahead genera-
tors are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead generator. Positive
logic equations for the DM74S182 are:
Cn + x = G0 + P0 Cn
Cn + y = G1 + P1 G0 + P1 P0 Cn
Cn + z = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 Cn
G = G3 (P3 + G2) (P3 + P2 + G1)
(P3 + P2 + P1 + G0)
P = P3 P2 P1 P0
Features
s Typical propagation delay time 7 ns
s Typical power dissipation 260 mW
Ordering Code:
Order Number Package Number
Package Description
DM74S182N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Pin Designations
Designation
G0, G1, G2, G3
P0, P1, P2, P3
Cn
Cn + x, Cn + y,
Cn + z
G
P
VCC
GND
Pin Nos.
3, 1, 14, 5
4, 2, 15, 6
13
12, 11, 9
Function
Active LOW
Carry Generate Inputs
Active LOW
Carry Propagate Inputs
Carry Input
Carry Outputs
10 Active LOW
Carry Generate Output
7 Active LOW
Carry Propagate Output
16 Supply Voltage
8 Ground
© 2000 Fairchild Semiconductor Corporation DS006474
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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| PDF Descargar | [ Datasheet DM74S182.PDF ] | |
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