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DM74S163 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DM74S163
Beschreibung Synchronous 4-Bit Binary Counters
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 8 Seiten
DM74S163 Datasheet, Funktion
February 1992
DM74S161 DM74S163
Synchronous 4-Bit Binary Counters
General Description
These synchronous presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs They are 4-bit binary counters The carry output is
decoded by means of a NOR gate thus preventing spikes
during the normal counting mode of operation Synchronous
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each
other when so instructed by the count enable inputs and
internal gating This mode of operation eliminates the output
counting spikes which are normally associated with asyn-
chronous (ripple clock) counters A buffered clock input trig-
gers the four flip-flops on the rising (positive-going) edge of
the clock input waveform
These counters are fully programmable that is the outputs
may be preset to either level As presetting is synchronous
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output Both count-
enable inputs (P and T) must be high to count and input T is
fed forward to enable the ripple carry output The ripple car-
ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the QA output This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages
Features
Y Synchronously programmable
Y Internal look-ahead for fast counting
Y Carry output for n-bit cascading
Y Synchronous counting
Y Load control line
Y Diode-clamped inputs
Connection Diagram
Dual-In-Line Package
Order Number DM74S161N or DM74S163N
See NS Package Number N16E
TL F 6471 – 1
C1995 National Semiconductor Corporation TL F 6471
RRD-B30M105 Printed in U S A






DM74S163 Datasheet, Funktion
Parameter Measurement Information
Switching Time Waveforms
TL F 6471 – 4
Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT
tr s 2 5 ns tf s 2 5 ns Vary PRR to measure fMAX
Note B Outputs QD and carry are tested at tn a 16 for S161 S163 where tn is the bit time when all outputs are low
Note C VREF e 1 5V
50X For S161 163
Switching Time Waveforms
Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT
Vary PRR to measure fMAX
Note B Enable P and enable T setup times are measured at tn a 0
Note C VREF e 1 5V
TL F 6471 – 5
50X tr s 2 5 ns tf s 2 5 ns
6

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