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DM74S163 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer DM74S163
Beschreibung Synchronous 4-Bit Binary Counters
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 7 Seiten
DM74S163 Datasheet, Funktion
August 1986
Revised April 2000
DM74S161 DM74S163
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. They are 4-bit binary counters. The carry output is
decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchro-
nous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with
each other when so instructed by the count enable inputs
and internal gating. This mode of operation eliminates the
output counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive-
going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a LOW level at the load input disables the
counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of
the enable input.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be HIGH to count, and
input T is fed forward to enable the ripple carry output. The
ripple carry output thus enabled will produce a HIGH-level
output pulse with a duration approximately equal to the
HIGH-level portion of the QA output. This HIGH-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages.
Features
s Synchronously programmable
s Internal look-ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s Diode-clamped inputs
Ordering Code:
Order Number
DM74S161N
DM74S163N
Package Number
Package Description
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006471
www.fairchildsemi.com






DM74S163 Datasheet, Funktion
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
VI Input Clamp Voltage
VCC = Min, II = −18 mA
VOH HIGH Level
Output Voltage
VCC = Min, IOH = Max
VIL = Max, VIH = Min
2.7
VOL LOW Level
VCC = Min, IOL = Max
Output Voltage
VIH = Min, VIL = Max
II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
IIH LOW Level
VCC = Max
CLK, Data
Input Current
VI = 2.7V
Others
10
IIL LOW Level
VCC = Max
Enable T
Input Current
VI = 0.5V
Others
IOS
Short Circuit Output Current
VCC = Max (Note 7)
40
ICC Supply Current
VCC = Max
Note 6: All typicals are at VCC = 5V, TA = 25°C.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Typ
(Note 6)
3.4
95
Max
1.2
0.5
1
50
200
4
2
100
160
Switching Characteristics
at VCC = 5V and TA = 25°C
RL = 280
Symbol
Parameter
From (Input)
CL = 15 pF
CL = 50 pF
To (Output)
Min Max Min Max
fMAX
tPLH
Maximum Clock Frequency
Propagation Delay Time
LOW-to-HIGH Level Output
40 35
Clock to Ripple Carry
25
25
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Ripple Carry
25
28
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
Clock to Any Q
15 15
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
Clock to Any Q
15 18
tPLH Propagation Delay Time
LOW-to-HIGH Level Output
Enable T to Ripple Carry
15
18
tPHL Propagation Delay Time
HIGH-to-LOW Level Output
Enable T to Ripple Carry
15
18
tPHL Propagation Delay Time
Clear to Any Q
HIGH-to-LOW Level Output (Note 8)
20 24
Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163.
Units
V
V
V
mA
µA
mA
mA
mA
Units
MHz
ns
ns
ns
ns
ns
ns
ns
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