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W523S99 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W523S99
Beschreibung HIGH FIDELITY PowerSpeech
Hersteller Winbond
Logo Winbond Logo 




Gesamt 14 Seiten
W523S99 Datasheet, Funktion
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W523SXX (PRELIMINARY)
HIGH FIDELITY PowerSpeechTM
GENERAL DESCRIPTION
The W523Sxx family are programmable speech synthesis ICs that utilize Winbonds new high fidelity
voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide
powerful user-programmable functions that make this chip suitable for an extremely wide range of
speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration
shown below:
PART
NO.
W523S08 W523S10 W523S12 W523S15 W523S20 W523S25 W523S30
Duration
8 sec.
10 sec.
12 sec.
15 sec.
20 sec.
25 sec.
30 sec.
PART
NO.
Duration
W523S40
40 sec.
W523S50
50 sec.
W523S60
60 sec.
W523S70
70 sec.
W523S80
80 sec.
W523S99 W523M02
100 sec. 120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output
New high fidelity synthesis algorithm
Either PWM mode or D/A converter mode can be selected for AUD output
Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs
Two trigger input debounce times (50 mS or 400 uS) can be set
Provides up to 2 LEDs and 5 STOP outputs
Flexible functions programmable through the following:
LD (Load), JP (Jump), MV (Move) and INC (Increase) commands
Four general purpose registers: R0, R1, R2 and R3
Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE
Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6
Speech equations
END instruction
Supports CPU interface operation
Symbolic compiler supported
Instruction cycle 400 µS typically
Section control for
Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000
- 1 - Revision A5






W523S99 Datasheet, Funktion
W523SXX (PRELIMINARY)
overwrite, or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the
triggers corresponding to each bit are shown above. “ X” indicates a “ don’ t care” bit.
The TG1, 2, 5, 6 represents triggers 1, 2, 5 and 6 respectively; the “R” represents the rising edge; and
“F” represents the falling edge. When any one of the eight bits is set to “1”, the rising or falling edge of
the corresponding trigger pin can be enabled, interrupting the current state.
5. STOP Register
BIT 7 6 5 4 3 2 1 0
STOP X X X STE STD STC STB STA
The STOP register stores stop output status information to determine the voltage level of each stop
output pin. The 8-bit structure of this register and the stop output pin corresponding to each bit are
show as above table. The “X” indicates a “don’ t care” bit. When a particular STOP bit is set to “1”, the
corresponding stop signal will be an active high output.
6. R0-R3 Registers
These four registers are 8-bit register that stores the entry values of from 0 to 255 voice groups. R0 is
a special register that can be incremented by "INC" instruction.
Option Control Function
There are four types of option control in W523Sxx. They can be determined by a declaration in the
users program file, but cannot be controlled by register.
FUNCTION
Page mode
configuration
Operation
mode
Oscillator
frequency
Voice
output type
MASK OPTION
DECLARATION
DEFINITION
DEFPAGE 1
256 interrupt vector/label for 1 page, 1 page in total (1-page mode)
DEFPAGE 8
256 interrupt vector/label for 1 page, 8 pages in total (8-page mode)
DEFPAGE 16 128 interrupt vector/label for 1 page, 16 pages in total (16-page mode)
DEFPAGE 32 64 interrupt vector/label for 1 page, 32 pages in total (32-page mode)
NORMAL
Normal mode operation
CPU
CPU mode operation
OSC_3MHz
3 MHz oscillator
OSC_1.5MHz 1.5 MHz oscillator
VOUT_DAC
DAC (AUD) output
VOUT_PWM PWM output
"DEFPAGE" determines the page operation mode in W523Sxx. The default setting of the page mode
is 1-page mode. The 8-page, 16-page or 32-page mode can be declared to extend the voice group
entry from 256 to 2047 in PowerSpeechprogram.
The W523Sxx can communicate with an external microprocessor through the simple serial CPU
interface, which is the same as the W583xx series. The CPU interface consists of the TG1, TG2, and
STPA/BUSY pins. "NORMAL" and "CPU" decide whether the operation mode of W523Sxx will be
normal mode or CPU mode.
"OSC_3MHz" and "OSC_1.5MHz" select the frequency of the system clock. "VOUT_DAC" and
"VOUT_PWM" select the voice output type.
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W523S99 pdf, datenblatt
W523SXX (PRELIMINARY)
PAD NO.
1
2
3
4
5
6
7
8
9
10
11
PAD NAME
VDD1
RESET
TEST
TG1
TG2
TG5
TG6
VSS1
LED1
STPA/BUSY
STPB
PAD NO.
12
13
14
15
16
17
18
19
PAD NAME
LED2/STPC
STPD
STPE
VSS2
VDD2
SPK-
AUD/SPK+
OSC
TYPICAL APPLICATION CIRCUIT
1. DAC output:
VDD (1.8V ~ 5.5V)
Rosc
VDD1 VDD2
OSC
LED1
TEST
STPA/BUSY
STPB
TG1
LED2/STPC
TG2 STPD
W523Sxx
TG5 STPE
TG6
AUD/SPK+
SPK-
/RESET VSS1 VSS2
LED 100 ohm
LED 100 ohm
Speaker
8 ohm
¼watt
NPN T’x
Cs Rs
Note:
1. In principle, the playing speed determined by Rosc should correspond to the sampling rate during the coding phase. The
playing speed may be adjusted by varing Rosc, however.
- 12 -

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