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PDF CYBL10461 Data sheet ( Hoja de datos )
| Número de pieza | CYBL10461 | |
| Descripción | Programmable Radio-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYBL10X6X Family Datasheet
Programmable Radio-on-Chip With
Bluetooth Low Energy (PRoC BLE)
General Description
PRoC BLE is a 32-bit, 48-MHz ARM® Cortex™-M0 BLE solution with CapSense®, 12-bit ADC, four timer, counter, pulse-width
modulators (TCPWM), thirty-six GPIOs, two serial communication blocks (SCBs), LCD, and I2S. PRoC BLE includes a royalty-free
BLE stack compatible with Bluetooth® 4.1 and provides a complete, programmable, and flexible solution for HID, remote controls,
toys, beacons, and wireless chargers. In addition to these applications, PRoC BLE provides a simple, low-cost way to add BLE
connectivity to any system.
Features
Bluetooth® Smart Connectivity
■ Bluetooth 4.1 single-mode device
■ 2.4-GHz BLE radio and baseband with integrated balun
■ TX output power: –18 dBm to +3 dBm
■ Received signal strength indicator (RSSI) with 1-dB resolution
■ RX sensitivity: –92 dBm
■ TX current: 15.6 mA at 0 dBm
■ RX current: 16.4 mA
ARM Cortex-M0 CPU Core
■ 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit
multiply, operating at up to 48 MHz
■ 128-KB flash memory
■ 16-KB SRAM memory
■ Emulated EEPROM using flash memory
■ Watchdog timer with dedicated internal low-speed oscillator
(ILO)
Ultra-Low-Power
■ 1.3-µA Deep-Sleep mode with watch crystal oscillator (WCO)
on
■ 150-nA Hibernate mode current with SRAM retention
■ 60-nA Stop mode current with GPIO wakeup
CapSense® Touch Sensing with Two-Finger Gestures
■ Up to 36 capacitive sensors for buttons, sliders, and touchpads
■ Two-finger gestures: scroll, inertial scroll, pinch, stretch, and
edge-swipe
■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (> 5:1) and liquid tolerance
■ Automatic hardware-tuning algorithm (SmartSense™)
Peripherals
■ 12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■ Ultra-low-power LCD segment drive for 128 segments with
operation in Deep-Sleep mode
■ Two serial communication blocks (SCBs) supporting I2C
(Master/Slave), SPI (Master/Slave), or UART
■ Four dedicated 16-bit TCPWMs
❐ Additional four 8-bit or two 16-bit PWMs
■ Programmable LVD from 1.8 V to 4.5 V
■ I2S Master interface
Clock, Reset, and Supply
■ Wide supply-voltage range: 1.9 V to 5.5 V
■ 3-MHz to 48-MHz internal main oscillator (IMO) with 2%
accuracy
■ 24-MHz external clock oscillator (ECO) without load capaci-
tance
■ 32-kHz WCO
Programmable GPIOs
■ 36 GPIOs configurable as open drain high/low,
pull-up/pull-down, HI-Z, or strong output
■ Any GPIO pin can be CapSense, LCD, or analog, with flexible
pin routing
Programming and Debug
■ 2-pin SWD
■ In-system flash programming support
Temperature and Packaging
■ Operating temperature range: –40 °C to +85 °C
■ Available in 56-pin QFN (7 mm × 7 mm) and 68-ball WLCSP
(3.52 mm × 3.91 mm) packages
PSoC® Creator™ Design Environment
■ Easy-to-use IDE to configure, develop, program, and test a
BLE application
■ Option to export the design to Keil, IAR, or Eclipse
Bluetooth Low Energy Protocol Stack
■ Bluetooth Low Energy protocol stack supporting generic
access profile (GAP) Central, Peripheral, Observer, or Broad-
caster roles
❐ Switches between Central and Peripheral roles on-the-go
■ Standard Bluetooth Low Energy profiles and services for
interoperability
❐ Custom profile and service for specific use cases
Errata: For information on silicon errata, see “Errata” on page 40. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90478 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 11, 2014
1 page  
PRELIMINARY
PRoC BLE: CYBL10X6X
Family Datasheet
An external active-LOW reset pin (XRES) can be used to reset
the device. The XRES pin has an internal pull-up resistor and, in
most applications, does not require any additional pull-up
resistors. The power system is described in detail in the “Power”
section on page 13.
Clock Control
The PRoC BLE clock control is responsible for providing clocks
to all subsystems and also for switching between different clock
sources without glitching. The clock control for PRoC BLE
consists of the IMO and the internal low-speed oscillator (ILO). It
uses the 24-MHz external crystal oscillator (ECO) and the
32-kHz WCO. In addition, an external clock may be supplied
from a pin.
The device has 12 dividers with 16 divider outputs. Two dividers
have additional fractional division capability. The HFCLK signal
is divided down, as shown in Figure 2, to generate the system
clock (SYSCLK) and peripheral clock (PERx_CLK) for different
peripherals. The system clock (SYSCLK) driving buses,
registers, and the processor must be higher than all the other
clocks in the system that are divided off HFCLK. The ECO and
WCO are present in the BLE subsystem and the clock outputs
are routed to the system resources.
Internal Main Oscillator (IMO)
The IMO is the primary system clock source, which can be
adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz. The
IMO accuracy is ±2%.
Internal Low-Speed Oscillator (ILO)
The ILO is a very-low-power 32-kHz oscillator, which is primarily
used to generate clocks for peripheral operations in Deep-Sleep
mode. The ILO-driven counters can be calibrated to the IMO to
improve accuracy. Cypress provides a software component,
which does the calibration.
Figure 2. Clock Control
ECO
Divider
/2n (n=0..3)
IMO
BLE
Subsystem
Prescaler
Divider 0
(/16)
HFCLK
SYSCLK
PER0_CLK
EXTCLK
Divider 9
(/16)
WCO
Fractional
Divider 0
(/16.5)
Fractional
Divider 1
(/16.5)
PER15_CLK
ILO LFCLK
External Crystal Oscillator (ECO)
The ECO is used as the active clock for the BLE subsystem to
meet the ±50-ppm clock accuracy requirement of the Bluetooth
4.1 specification. The ECO includes a tunable load capacitor to
tune the crystal clock frequency by measuring the actual clock
frequency. The high-accuracy ECO clock can also be used as a
system clock.
Watch Crystal Oscillator (WCO)
The WCO is used as the sleep clock for the BLE subsystem to
meet the ±500-ppm clock accuracy requirement of the Bluetooth
4.1 specification. The sleep clock provides accurate sleep timing
and enables wakeup at specified advertisement and connection
intervals. With the WCO and firmware, an accurate real-time
clock (within the bounds of the 32.768-kHz crystal accuracy) can
be realized.
Voltage Reference
The internal bandgap reference circuit with 1% accuracy
provides the voltage reference for the 12-bit SAR ADC. To
enable better SNRs and absolute accuracy, it will be possible to
bypass the internal bandgap reference using a REF pin and to
use an external reference for the SAR.
Watchdog Timer (WDT)
A watchdog timer is implemented in the system resources
subsystem running from the ILO; this allows watchdog opera-
tions during Deep-Sleep mode and generates a watchdog reset
if not serviced before the timeout occurs. The watchdog reset is
recorded in the ‘Reset Cause’ register.
Peripheral Blocks
12-Bit SAR ADC
The ADC is a 12-bit, 1-Msps SAR ADC with a built-in
sample-and-hold (S/H) circuit. The ADC can operate with either
an internal voltage reference or an external voltage reference.
Preceding the SAR ADC is the SARMUX, which can route
external pins and internal signals (analog mux bus and temper-
ature sensor output) to the eight internal channels of the SAR
ADC. The sequencer controller (SARSEQ) is used to control the
SARMUX and SAR ADC to do an automatic scan on all enabled
channels without CPU intervention and for preprocessing tasks
such as averaging the output data. A Cypress-supplied software
driver (Component) is used to control the ADC peripheral.
Figure 3. SAR ADC System Diagram
Control
VPLUS
SARMUX
V MINUS
SARADC
Data
Configure
R egister s
SARSEQ
S equencer
AHB, DSI
SARREF
Document Number: 001-90478 Rev. *F
Analog Mux
Bus A/B
Vrefs
Ref-bypass
Page 5 of 42
5 Page 
PRELIMINARY
PRoC BLE: CYBL10X6X
Family Datasheet
Table 2. CYBL10X6X Pin List (WLCSP Package) (continued)
Pin
Name
Type
H5
VSSR
GROUND Radio ground
Description
H6
VSSR
GROUND Radio ground
H7
ANT
ANTENNA Antenna pin
J1
P0.4
GPIO
Port 0 Pin 4, analog/digital/lcd/csd
J2
P0.0
GPIO
Port 0 Pin 0, analog/digital/lcd/csd
J3
VDDR
POWER 1.9-V to 5.5-V radio supply
J6
VDDR
POWER 1.9-V to 5.5-V radio supply
J7 NO CONNECT
-
The I/O subsystem consists of a high-speed I/O matrix (HSIOM), which is a group of high-speed switches that routes GPIOs to the
resources inside the device. These resources include CapSense, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are
32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are assigned to each GPIO
in the port. This provides up to 16 different options for GPIO routing as shown in Table 3.
Table 3. HSIOM Port Settings
Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Description
Firmware-controlled GPIO
Reserved
Reserved
Reserved
Pin is a CSD sense pin
Pin is a CSD shield pin
Pin is connected to AMUXA
Pin is connected to AMUXB
Pin-specific Active function #0
Pin-specific Active function #1
Pin-specific Active function #2
Reserved
Pin is an LCD common pin
Pin is an LCD segment pin
Pin-specific Deep-Sleep function #0
Pin-specific Deep-Sleep function #1
The selection of peripheral functions for different GPIO pins is given in Table 4.
Table 4. Port Pin Connections
Digital (HSIOM_PORT_SELx.SELy) ('x' denotes port number and 'y' denotes pin number)
Name
Analog
0
8
9 10 14
15
P0.0
GPIO Active #0
GPIO TCPWM0_P[3]
Active #1
SCB1_UART_RX[1]
Active #2
Deep Sleep #0
Deep Sleep #1
SCB1_I2C_SDA[1] SCB1_SPI_MOSI[1]
P0.1
GPIO TCPWM0_N[3] SCB1_UART_TX[1]
SCB1_I2C_SCL[1] SCB1_SPI_MISO[1]
P0.3
GPIO TCPWM1_N[3] SCB1_UART_CTS[1]
SCB1_SPI_SCLK[1]
P0.4
P0.5
GPIO TCPWM1_P[0] SCB0_UART_RX[1]
GPIO TCPWM1_N[0] SCB0_UART_TX[1]
EXT_CLK[0]/
ECO_OUT[0]
SCB0_I2C_SDA[1] SCB0_SPI_MOSI[1]
SCB0_I2C_SCL[1] SCB0_SPI_MISO[1]
Document Number: 001-90478 Rev. *F
Page 11 of 42
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