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NTD40N03R
Power MOSFET
45 A, 25 V, N−Channel DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low RDS(on) to Minimize Conduction Loss
• Low Ciss to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• These are Pb−Free Devices
MAXIMUM RATINGS (TJ = 25°C unless otherwise specified)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C, Chip
− Continuous @ TA = 25°C, Limited by Wires
− Single Pulse (tp ≤ 10 ms)
Thermal Resistance − Junction−to−Ambient
(Note 1)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
Thermal Resistance − Junction−to−Ambient
(Note 2)
− Total Power Dissipation @ TA = 25°C
− Drain Current − Continuous @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
RPqDJC
ID
ID
ID
RqJA
PD
ID
RqJA
PD
ID
TJ, Tstg
25
±20
3.0
50
45
32
100
71.4
2.1
9.2
100
1.5
7.8
−55 to
175
Vdc
Vdc
°C/W
W
A
A
A
°C/W
W
A
°C/W
W
A
°C
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq. in pad size.
2. When surface mounted to an FR4 board using minimum recommended
pad size.
http://onsemi.com
45 AMPERES, 25 VOLTS
RDS(on) = 12.6 mW (Typ)
N−CHANNEL
D
G
S
4
4
12
3
CASE 369AA
DPAK
(Surface Mount)
STYLE 2
1
2
3
CASE 369D
DPAK
(Straight Lead)
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4 Drain
4 Drain
1
Gate
2
Drain
3
Source
1
Gate
2
Drain
3
Source
Y
WW
T40N03
G
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 7
1
Publication Order Number:
NTD40N03R/D