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HCF40103B Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer HCF40103B
Beschreibung 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
Hersteller STMicroelectronics
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Gesamt 13 Seiten
HCF40103B Datasheet, Funktion
HCC/HCF40102B
HCC/HCF40103B
8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
40102B 2-DECADE BCD TYPE
40103B 8-BIT BINARY TYPE
. SYNCHRONOUS OR ASYNCHRONOUS
PRESET
. MEDIUM-SPEED OPERATION : fCL = 3.6MHz
(TYP.) @ VDD = 10V
. CASCADABLE
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 5V, 10V AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100 nA AT 18V AND 25°C
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No. 13 A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
DESCRIPTION
The HCC40102B, HCC40103B, (extended tempera-
ture range) and the HCF40102B, HCF40103B (inter-
mediate temperature range) are monolithic integrated
circuits, available in 16-lead dual in-line plastic or ce-
ramic package. The HCC/HCF40102B, and
HCC/HCF40103B consist of an 8-stage synchronous
down counter with a single output which is active when
the internal count is zero. The HCC/HCF40102B is
configured as two cascaded 4-bit BCD counters, and
the HCC/HCF40103B contains a single 8-bit binary
counter. Each type has control inputs for enabling or
disabling the clock, for clearing the counter to its
maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETEC
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the
JAM input is clocked into the counter on the next
positive clock transition regardless of the state of the
CI/CE input. When the ASYNCHRONOUS
PRESET-ENABLE (APE) input is low, data at the
June 1989
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC401XXBF HCF401XXBEY
HCF401XXBC1
PIN CONNECTIONS
1/13






HCF40103B Datasheet, Funktion
HCC/HCF40102B/40103B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25°C, CL = 50pF, RL = 200k,
typical temperature coefficient for all VDD values is 0.3%/°C, all input rise and fall time = 20ns)
Symbol
Parameter
t PHL,
tPLH
Propagation
Delay Time
Clock to-out
Test Conditions
V al ue
V D D (V) Min. Typ. Max.
5 300 600
10 130 260
15 95 190
Carry In/Counter
Enable-to-output
5 200 400
10 90 180
15 65 130
Asynchronous
Preset
Enable-to-output
Clear-to-output
5 650 1300
10 300 600
15 200 400
5 375 750
10 180 360
t THL , tT L H Transition Time
15 100 200
5 100 200
10 50 100
15 40 80
tW Pulse Width Clock Pulse
Width
5 300 150
10 180 90
CLR Pulse
Width
15 80 40
5 320 160
10 160 80
APE Pulse Width
15 100 50
5 360 180
t se t u p Setup Time
SPE Setup Time
JAM Setup Time
10 160 80
15 120 60
5 280 140
10 140 70
15 100 50
5 200 100
10 80 40
15 60 30
fCL Maximum Clock Input Frequency
5 0.7 1.4
10 1.8 3.6
15 2.4 4.8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
6/13

6 Page









HCF40103B pdf, datenblatt
HCC/HCF40102B/40103B
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
12/13
P027A

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