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74HCT04-Q100 Schematic ( PDF Datasheet ) - NXP Semiconductors
| Teilenummer | 74HCT04-Q100 |
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| Beschreibung | Hex inverter | |
| Hersteller | NXP Semiconductors | |
| Logo |  |
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Gesamt 16 Seiten 
74HC04-Q100; 74HCT04-Q100
Hex inverter
Rev. 2 — 10 April 2013
Product data sheet
1. General description
The 74HC04-Q100; 74HCT04-Q100 is a hex inverter. Inputs also include clamp diodes,
this enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Complies with JEDEC standard JESD8-1A
Input levels:
For 74HC04-Q100: CMOS level
For 74HCT04-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
 
NXP Semiconductors
74HC04-Q100; 74HCT04-Q100
Hex inverter
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
ICC
supply current VI = VCC or GND; IO = 0 A;
-
-2
-
20
-
40 A
VCC = 5.5 V
ICC additional
per input pin;
- 120 432
-
540
-
590 A
supply current VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI input
capacitance
- 3.5 -
-
-
-
- pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; CL = 50 pF; for load circuit see Figure 7.
Symbol Parameter
Conditions
25 C
Min Typ
74HC04-Q100
tpd propagation delay nA to nY; see Figure 6
[1]
VCC = 2.0 V
-
VCC = 4.5 V
-
VCC = 5.0 V; CL = 15 pF
-
VCC = 6.0 V
tt
transition time
see Figure 6
-
[2]
VCC = 2.0 V
-
VCC = 4.5 V
-
VCC = 6.0 V
-
CPD power dissipation per package; VI = GND to VCC [3] -
capacitance
74HCT04-Q100
tpd propagation delay nA to nY; see Figure 6
[1]
VCC = 4.5 V
-
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
CPD power dissipation per package;
capacitance
VI = GND to VCC 1.5 V
-
[2] -
[3] -
25
9
7
7
19
7
6
21
10
8
7
24
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
74HC_HCT04_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 April 2013
Max
85
17
-
14
75
15
13
-
19
-
15
-
40 C to +125 C Unit
Max Max
(85 C) (125 C)
105 130 ns
21 26 ns
- - ns
18 22 ns
95 110 ns
19 22 ns
16 19 ns
- - pF
24 29 ns
- - ns
19 22 ns
- - pF
© NXP B.V. 2013. All rights reserved.
6 of 16
6 Page 
NXP Semiconductors
74HC04-Q100; 74HCT04-Q100
Hex inverter
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
SOT762-1
D BA
terminal 1
index area
A
A1
E
c
detail X
terminal 1
index area
L
e
2
1
Eh
14
e1
b
6
vM C AB
wM C
7
e
8
y1 C
C
y
13 9
Dh
0 2.5
5 mm
X
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c D(1) Dh E(1) Eh e e1 L
v
w
y y1
mm
1
0.05 0.30
0.00 0.18
0.2
3.1 1.65
2.9 1.35
2.6
2.4
1.15
0.85
0.5
2
0.5
0.3
0.1 0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT762-1
---
MO-241
---
ISSUE DATE
02-10-17
03-01-27
Fig 11. Package outline SOT762-1 (DHVQFN14)
74HC_HCT04_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 April 2013
© NXP B.V. 2013. All rights reserved.
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