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G084SN03-V2 Schematic ( PDF Datasheet ) - AUO

Teilenummer G084SN03-V2
Beschreibung SVGA Color TFT LCD Module
Hersteller AUO
Logo AUO Logo 




Gesamt 26 Seiten
G084SN03-V2 Datasheet, Funktion
Version: 0.3
Total Pages: 26
Date: 2005/8/29
Product Functional Specification
8.4 inch SVGA Color TFT LCD Module
Model Name: G084SN03 V.2
(u) Preliminary Specification
( ) Final Specification
Note: This Specification is subject to change without notice
(C) Copyright AU Optroncis, Inc.
2005 All Right Reserved.
No Reproduction and Redistribution Allowed.
G084SN03 V.2
8/29






G084SN03-V2 Datasheet, Funktion
2.2 Functional Block Diagram
The following diagram shows the functional block of the 8.4 inches Color TFT LCD
Module
(C) Copyright AU Optroncis, Inc.
2005 All Right Reserved.
No Reproduction and Redistribution Allowed.
G084SN03 V.2
8/29

6 Page









G084SN03-V2 pdf, datenblatt
Signal Name
Description
+RED5
Red Data 5 (MSB)
+RED4
Red Data 4
+RED3
Red Data 3
+RED2
Red Data 2
+RED1
Red Data 1
+RED0
Red Data 0 (LSB)
Red-pixel Data
+GREEN5
Green Data 5 (MSB)
+GREEN4
Green Data 4
+GREEN3
Green Data 3
+GREEN2
Green Data 2
+GREEN1
Green Data 1
+GREEN0
Green Data 0 (LSB)
Green-pixel Data
+BLUE5
Blue Data 5 (MSB)
+BLUE4
Blue Data 4
+BLUE3
Blue Data 3
+BLUE2
Blue Data 2
+BLUE1
Blue Data 1
+BLUE0
Blue Data 0 (LSB)
Blue-pixel Data
CLK Data Clock
DE Display Timing
VSYNC
HSYNC
Vertical Sync
Horizontal Sync
Red-pixel Data
Each red pixels brightness data consists of these
6 bits pixel data.
Green-pixel Data
Each green pixels brightness data consists of these
6 bits pixel data.
Blue-pixel Data
Each blue pixels brightness data consists of these
6 bits pixel data.
The typical frequency is 40MHz. The signal is
used to strobe the pixel data and DE signals.
All pixel data shall be valid at the falling edge when
the DE signal is high.
This signal is strobed at the falling edge of CLK.
When the signal is high, the pixel data shall be valid
to be displayed.
The signal is synchronized to CLK.
The signal is synchronized to CLK.
NoteOutput signals from any system shall be low or Hi-Z state when VDD is off.
(C) Copyright AU Optroncis, Inc.
2005 All Right Reserved.
No Reproduction and Redistribution Allowed.
G084SN03 V.2
8/29

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SeitenGesamt 26 Seiten
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