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PDF MV6601C Data sheet ( Hoja de datos )
| Número de pieza | MV6601C | |
| Descripción | multi-core processor | |
| Fabricantes | Mavrix | |
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MV6601C Datasheet
MVD-6601-04-DS-EN
Version: 0.7
May 2008
1 page  
MV6601C Data Sheet(V0.7)
Revision History
Date
2007/07/05
2007/07/06
2007/07/09
2007/07/11
2008/05/10
2008/05/12
Version
0.1
0.2
0.3
0.4
0.6
0.7
Description
Initial Draft
Added Boot Up Sequence, Overview, Group Connection
Diagram.
Modified Tables, Pin assignment, Pin Description
Remove Section 1.3 Advance Feature List,
Modify Pin Description, Makes viewable graphics
Edit Acronym and Abbreviations
Update
Update
MVD-6601-04-DS-EN
Mavrix Confidential
http://www.mavrixtech.com
Page 5 of 48
5 Page 
MV6601C Data Sheet(V0.7)
4.4 Host Interface
The MV6601C provides various host interfaces which allows an external master to
connect to MV6601C. By the software level, a pair of software API will be implemented
inside the MV6601C SoC and the host processor (We call the software run at the host
processor as “HIF” supplied by Mavrix). Commands from host will be sent to MV6601C,
explained and executed by MV6601C, and also information inside MV6601C will be
obtained by the host.
Briefly, it is the main interface which exchanges data by MV6601C to help our customer
to integrate whole MV6601C function. Media streaming is also send to MV6601C for
viewing by the host interface.
The MV6601C supports multiple types of serial host interface and one parallel interface.
The CPU interprets the host commands, performs corresponding operations and then
sends the status back to the host processor.
Optionally, MV6601C also output one level-trigger signal to interrupt the host. (INTR)
The MV6601C supports the following types of host interfaces:
l I2C (slave)
l SPI (slave, mode 0/1/2/3)
l UART
l LCM-like 8-bit I80 interface
Note: The data field may contain multiple bytes when necessary.
Note: Multiple bytes data is transfer by Little-Endian that is low byte transferred first.
Note: Since MV6601C RISC is based on 32bit access, all data bytes after the addresses
are treated as 4-chained bytes. That is, the API in the host processor will group 4
consecutive bytes access together as a single 32bit access.
MVD-6601-04-DS-EN
Mavrix Confidential
http://www.mavrixtech.com
Page 11 of 48
11 Page | ||
| Páginas | Total 48 Páginas | |
| PDF Descargar | [ Datasheet MV6601C.PDF ] | |
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