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XS1-L02A-QF124 Schematic ( PDF Datasheet ) - Xmos

Teilenummer XS1-L02A-QF124
Beschreibung Dual-Tile Multicore Microcontroller
Hersteller Xmos
Logo Xmos Logo 




Gesamt 25 Seiten
XS1-L02A-QF124 Datasheet, Funktion
XS1-L02A-QF124 Datasheet
2012/10/12
XMOS © 2012, All Rights Reserved
Document Number: X1189,






XS1-L02A-QF124 Datasheet, Funktion
XS1-L02A-QF124 Datasheet
5
Module
Tile 0 I/O
Tile 1 I/O
Name
X0D18
X0D19
X0D20
X0D21
X0D22
X0D23
X0D24
X0D25
X0D26
X0D27
X0D28
X0D29
X0D30
X0D31
X0D32
X0D33
X0D34
X0D35
X0D36
X0D37
X0D38
X0D39
X0D40
X0D41
X0D42
X0D43
X1D00
X1D01
X1D02
X1D03
X1D04
X1D05
X1D06
X1D07
X1D08
X1D09
X1D10
X1D11
X1D12
X1D13
X1D14
X1D15
X1D16
X1189,
Function
XLB02bi /5b
P4D2 P8B4 P16A12
XLB12bi /5b
P4D3 P8B5 P16A13
XLB25ib
P4C2 P8B6 P16A14 P32A30
XLB35ib
P4C3 P8B7 P16A15 P32A31
XLB45ib
P1G0
P1H0
P1I0
P1J0
P4E0 P8C0 P16B0
P4E1 P8C1 P16B1
P4F0 P8C2 P16B2
P4F1 P8C3 P16B3
P4F2 P8C4 P16B4
P4F3 P8C5 P16B5
P4E2 P8C6 P16B6
P4E3 P8C7 P16B7
P1K0
P1L0
P1M0
P8D0 P16B8
P1N0
P8D1 P16B9
P1O0
P8D2 P16B10
P1P0
P8D3 P16B11
P8D4 P16B12
P8D5 P16B13
P8D6 P16B14
P8D7 P16B15
P1A0
XLA45ob P1B0
XLA35ob
P4A0 P8A0 P16A0
XLA25ob
P4A1 P8A1 P16A1
XLA12bo/5b
P4B0 P8A2 P16A2
XLA02bo/5b
P4B1 P8A3 P16A3
XLA02bi /5b
P4B2 P8A4 P16A4
XLA12bi /5b
P4B3 P8A5 P16A5
XLA25ib
P4A2 P8A6 P16A6
XLA35ib
P4A3 P8A7 P16A7
XLA45ib P1C0
P1D0
P32A20
P32A21
P32A22
P32A23
P32A24
P32A25
P32A26
P32A27
P1E0
XLB45ob
P1F0
XLB35ob
P4C0 P8B0 P16A8 P32A28
XLB25ob
P4C1 P8B1 P16A9 P32A29
XLB12bo/5b
P4D0 P8B2 P16A10
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Active
Properties
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PUS, RU
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS
PDS
PDS, RU
PDS, RU
PDS, RU
PDS, RU
PDS, RU
(continued)

6 Page









XS1-L02A-QF124 pdf, datenblatt
XS1-L02A-QF124 Datasheet
11
Figure 4:
Boot source
pins
MODE[4] MODE[3] MODE[2] Boot Source
X 0 0 None: Device waits to be booted via JTAG
X 0 1 Reserved
0 1 0 X0 boots from link B, X1 from channel end 0 via X0
X0 boots from SPI, X1 from channel end 0 via X0
PinA
Signal Description
0 1 1 X0D00 MISO Master In Slave Out
X0D01 SS
Slave Select
X0D10 SCLK Clock
X0D11 MOSI Master Out Slave In
1 1 0 X0 and X1 independently enable link B and internal
links (E, F, G, H), and boot from channel end 0
1 1 1 Both tiles boot from SPI independently
A The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. An SPI boot
program can be burned into OTP and used at any time.
X1189,
5.7 OTP
Each xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with
a security register that configures system wide security features. The OTP holds
data in 2k rows x 32-bit configuration which can be used to implement secure
bootloaders and store encryption keys. Data for the security register is loaded
from the OTP on power up. All additional data in OTP is copied from the OTP to
SRAM and executed first on the processor.
5.7.1 Security Register
The security register enables the following security features:
· Secure Boot: The xCORE Tile is forced to boot from address 0 of the OTP,
allowing the xCORE Tile boot ROM to be bypassed (see §5.6). This feature can
be used to implement a secure bootloader which loads an encrypted image from
external flash, decrypts and CRC checks it with the processor, and discontinues
the boot process if the decryption or CRC check fails. XMOS provides a default
secure bootloader that can be written to the OTP along with secret decryption
keys.
· Disable JTAG: The JTAG interface is disabled, making it impossible for the tile
state or memory content to be accessed via the JTAG interface.
· Disable Link access: Other tiles are forbidden access to the processor state via
the system switch.
Disabling both JTAG and Link access transforms an xCORE Tile into a “secure
island” with other tiles free for non-secure user application code.
· Disable Global Debug access: Disables access to the DEBUG_N pin.

12 Page





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