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NOIL2SC1300A-GDC Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NOIL2SC1300A-GDC
Beschreibung High Speed CMOS Image Sensor
Hersteller ON Semiconductor
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NOIL2SC1300A-GDC Datasheet, Funktion
NOIL2SM1300A
LUPA1300-2: High Speed
CMOS Image Sensor
Features
1280 x 1024 Active Pixels
14 mm X 14 mm Square Pixels
1.4” Optical Format
Monochrome or Color Digital Output
500 fps Frame Rate
On-Chip 10-Bit ADCs
12 LVDS Serial Outputs
Random Programmable ROI Readout
Pipelined and Triggered Global Shutter
On-Chip Column FPN Correction
Serial Peripheral Interface (SPI)
Limited Supplies: Nominal 2.5 V and 3.3 V
50°C to +85°C Operational Temperature Range
168-Pin mPGA Package
Power Dissipation: 1350 mW
These Devices are PbFree and are RoHS Compliant
Applications
High Speed Machine Vision
Motion Analysis
Intelligent Traffic System
Medical Imaging
Industrial Imaging
Description
The LUPA1300-2 is an integrated SXGA high speed, high
sensitivity CMOS image sensor. This sensor targets high
speed machine vision and industrial monitoring
applications. The LUPA1300-2 sensor runs at 500 fps and
has triggered and pipelined shutter modes. It packs 24
parallel 10-bit A/D converters with an aggregate conversion
rate of 740 MSPS. On-chip digital column FPN correction
enables the sensor to output ready to use image data for most
applications. To enable simple and reliable system
integration, the 12 channels, 1 sync channel, 8 Gbps, and
LVDS serial link protocol supports skew correction and
serial link integrity monitoring.
The peak responsivity of the 14 mm x 14 mm 6T pixel is
63 DN/nJ/cm2. Dynamic range is measured at 57 dB. In full
frame video mode, the sensor consumes 1350 mW from the
2.5 V and 3.3 V power supplies. The sensors integrate A/D
http://onsemi.com
Figure 1. LUPA13002 Die Photo
conversion, on-chip timing for a wide range of operating
modes, and has an LVDS interface for easy system
integration.
By removing the visually disturbing column patterned
noise, this sensor enables building a camera without any
offline correction or the need for memory. In addition, the
on-chip column FPN correction is more reliable than an
offline correction, because it compensates for supply and
temperature variations. The sensor requires one master
clock for operations up to 500 fps.
The LUPA1300-2 is housed in a 168 pin mPGA package
and is available in a monochrome version and Bayer (RGB)
patterned color filter array. The monochrome version is also
available without glass. Contact your local
ON Semiconductor office.
© Semiconductor Components Industries, LLC, 2014
June, 2014 Rev. 10
1
Publication Order Number:
NOIL2SM1300A/D






NOIL2SC1300A-GDC Datasheet, Funktion
NOIL2SM1300A
Table 6. AC ELECTRICAL CHARACTERISTICS (Note 1)
The following specifications apply for VDD = 2.5 V, Clock = 315 MHz, 500 fps.
Symbol
FCLK
DCCLK
DCD
fps
Parameter
Input Clock Frequency
Clock Duty Cycle
Duty Cycle Distortion
Jitter
Frame Rate
Condition
fps = 500
At maximum clock
At maximum clock
peak-to-peak
Maximum clock speed
Typ Max Units
315 MHz
50 %
250 ps
50 ps
500 fps
NOTE: Duty Cycle Distortion and Jitter is passed directly from input to output. Therefore, DCD and Jitter tolerance depends on the
customer’s system clock generation circuitry.
OVERVIEW
This data sheet describes the interface of the LUPA1300-2
image sensor. The SXGA resolution CMOS active pixel
sensor features synchronous shutter and a maximal frame
rate of 500 fps in full resolution. The readout speed is
boosted by sub sampling and the windowed region of
interest (ROI) readout. FPN correction cannot be used in
conjunction with sub-sampling and windowed region of
interest readout for windows starting with non zero kernel
address. High dynamic range scenes can be captured using
the double and multiple slope functionality. User
programmable row and column start and stop positions
enables windowing. Sub sampling reduces resolution while
maintaining the constant field of view and an increased
frame rate.
The LUPA1300-2 sensor has 12 LVDS high speed outputs
that transfer image data over longer distances. This
simplifies the surrounding system. The LVDS interface can
receive high speed and wide bandwidth data signals and
maintain low noise and distortion. A special training mode
enables the receiving system to synchronize the incoming
data stream when switching to master, slave, or triggered
mode. The image sensor also integrates a programmable
offset and gain amplifier for each channel.
A 10-bit ADC converts the analog signal to a 10-bit digital
word stream. The sensor uses a 3-wire Serial Peripheral
Interface (SPI). It requires only one master clock for
operation up to 500 fps.
The sensor is available in a monochrome version or Bayer
(RGB) patterned color filter array. It is placed in a 168-pin
ceramic mPGA package.
Figure 2 depicts the photovoltaic response of the
LUPA13002. Figure 3 shows the spectral response for the
mono and color versions of LUPA1300-2.
Photovoltaic Response Curve
Figure 3. Photovoltaic Response of LUPA13002
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NOIL2SC1300A-GDC pdf, datenblatt
NOIL2SM1300A
Table 9. INTERNAL REGISTERS
Block
Register Name Address [6..0]
Data Block datachannel0_2
31
datachannel1_1
32
datachannel1_2
33
Field
[7:0]
[0]
[1]
[2]
[3]
[5:4]
[7:0]
Reset Value
0x00
0
0
0
0
0x00
0x00
Description
Pattern inserted to generate a test image
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the testpat
register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
datachan-
nel12_1
datachan-
nel12_2
Sequencer seqmode1
seqmode2
seqmode3
54 [0] 0
Bypass the data block
[1] 0
Enables the FPN correction
[2] 0
Overwrite incoming ADC data by the data in the testpat
register
[3] 0
Reserved, fixed value
[5:4] 0x00
Pattern inserted to generate a test image
55 [7:0] 0x00 Pattern inserted to generate a test image
56 [0] 1
Enables sequencer for image capture
[1] 1
‘1’: Master mode, integration timing is generated on-chip
‘0’: Slave mode, integration timing is controlled off-chip
through INT_TIME1, INT_TIME2 and INT_TIME3 pins
[2] 0
‘0’: Pipelined mode
‘1’: Triggered mode
[3] 0
Enables(‘1’)/disables(‘0’) subsampling
[4] 0
‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0
‘0’: B&W subsampling scheme: 1:0:1:0:1
[5] 0
Enable dual slope
[6] 0
Enable triple slope
[7] 0
Enables continued row select (that is, assert row select
during pixel read out)
57
[4:0] ‘10000’
Must be overwritten with ‘10001’ to this register after
startup, before readout.
[6:5] ‘00’
Number of active windows:
“00”: 1 window
“01”: 2 windows
“10”: 3 windows
“11”: 4 windows
58 [0] ‘1’
Enables the generation of the CRC10 on the data and sync
channels
[1] ‘0’
Enable readout black/grey columns
[2] ‘0’
Enable column fpn calibration/enable readout dummy line
[5:3] “001”
Number of frames in nondestructive read out:
“000”: invalid
“001”: one reset, one sample (default mode)
“010”: one reset, two samples
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