PDF NOIL2SM1300A Data sheet ( Hoja de datos )

Número de pieza	NOIL2SM1300A
Descripción	High Speed CMOS Image Sensor
Fabricantes	ON Semiconductor
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No Preview Available ! NOIL2SM1300A LUPA1300-2: High Speed CMOS Image Sensor Features • 1280 x 1024 Active Pixels • 14 mm X 14 mm Square Pixels • 1.4” Optical Format • Monochrome or Color Digital Output • 500 fps Frame Rate • On-Chip 10-Bit ADCs • 12 LVDS Serial Outputs • Random Programmable ROI Readout • Pipelined and Triggered Global Shutter • On-Chip Column FPN Correction • Serial Peripheral Interface (SPI) • Limited Supplies: Nominal 2.5 V and 3.3 V • −50°C to +85°C Operational Temperature Range • 168-Pin mPGA Package • Power Dissipation: 1350 mW • These Devices are Pb−Free and are RoHS Compliant Applications • High Speed Machine Vision • Motion Analysis • Intelligent Traffic System • Medical Imaging • Industrial Imaging Description The LUPA1300-2 is an integrated SXGA high speed, high sensitivity CMOS image sensor. This sensor targets high speed machine vision and industrial monitoring applications. The LUPA1300-2 sensor runs at 500 fps and has triggered and pipelined shutter modes. It packs 24 parallel 10-bit A/D converters with an aggregate conversion rate of 740 MSPS. On-chip digital column FPN correction enables the sensor to output ready to use image data for most applications. To enable simple and reliable system integration, the 12 channels, 1 sync channel, 8 Gbps, and LVDS serial link protocol supports skew correction and serial link integrity monitoring. The peak responsivity of the 14 mm x 14 mm 6T pixel is 63 DN/nJ/cm2. Dynamic range is measured at 57 dB. In full frame video mode, the sensor consumes 1350 mW from the 2.5 V and 3.3 V power supplies. The sensors integrate A/D http://onsemi.com Figure 1. LUPA1300−2 Die Photo conversion, on-chip timing for a wide range of operating modes, and has an LVDS interface for easy system integration. By removing the visually disturbing column patterned noise, this sensor enables building a camera without any offline correction or the need for memory. In addition, the on-chip column FPN correction is more reliable than an offline correction, because it compensates for supply and temperature variations. The sensor requires one master clock for operations up to 500 fps. The LUPA1300-2 is housed in a 168 pin mPGA package and is available in a monochrome version and Bayer (RGB) patterned color filter array. The monochrome version is also available without glass. Contact your local ON Semiconductor office. © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 10 1 Publication Order Number: NOIL2SM1300A/D 1 page NOIL2SM1300A Table 4. POWER SUPPLY RATINGS (Notes 1, 2 and 3) Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. Clock = 315 MHz Symbol Power Supply Parameter Condition Min Typ Max Units VRES_AB (Note 4) Antiblooming Supply Operating Voltage Dynamic Current Clock enabled, lux = 0 -10% 0.7 +10% V 1 mA Peak Current following edge reset Clock enabled, lux = 0 50 mA Standby Current Shutdown mode, lux = 0 1 mA VRES_DS Reset Dual Slope Supply Operating Voltage Dynamic Current Clock enabled, lux = 0 1.8 2.5 3.675 V 0.4 3 mA Peak Current Clock enabled, lux = 0 36 mA VRES_TS Reset Triple Slope Supply Operating Voltage Dynamic Current Clock enabled, lux = 0 1.8 2.2 3.675 V 0.3 2 mA Peak Current Clock enabled, lux = 0 14 mA VMEM_L Memory Element Operating Voltage low level supply Dynamic Current Clock enabled, lux = 0 -5% 2.5 +5% V 0.2 1 mA Peak Current during FOT Clock enabled, lux = 0 62 mA Peak Current during FOT Clock enabled, bright 30 mA VMEM_H Memory Element Operating Voltage high level supply Dynamic Current Clock enabled, lux = 0 -5% 3.3 +5% V 1 mA Peak Current during FOT Clock enabled, lux = 0 45 mA VPRECH (Note 4) Pre_charge Driver Supply Operating Voltage Dynamic Current Clock enabled, lux = 0 -10% 0.7 +10% V 0.3 3 mA Peak Current during FOT Clock enabled, lux = 0 32 mA Peak Current during FOT Clock enabled, lux = bright 25 mA 1. All parameters are characterized for DC conditions after thermal equilibrium is established. 2. The peak currents were measured without the load capacitor from the LDO (Low Dropout Regulator). The 100 nF capacitor bank was connected to the pin in question. 3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance circuit. 4. The VRES_AB and VPRECH power supply should be designed to have a sourcing and sinking current capability for frame rates of the order of 20k frames /sec. Every module in the image sensor has its own power supply and ground. The grounds can be combined externally, but not all power supply inputs may be combined. Some power supplies must be isolated to reduce electrical crosstalk and improve shielding, dynamic range, and output swing. Internal to the image sensor, the ground lines of each module are kept separate to improve shielding and electrical crosstalk between them. The LUPA1300-2 contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, take normal precautions to avoid voltages higher than the maximum rated voltages in this high impedance circuit. Unused inputs must always be tied to an appropriate logic level, for example, VDD or GND. All cap_xxx pins must be connected to ground through a 100 nF capacitor. The recommended combinations of supplies are: • Analog group of +2.5 V supply: VSAMPLE, VRES_DS, VMEM_L, VADC, Vpix, VANA, VBUF • Digital Group of +2.5 V supply: VDIG, VLVDS • Combine VPRECH and VRES_AB to one supply (Note 4) Table 5. POWER DISSIPATION (Note 1) Power supply specifications according to Table 4. Symbol Parameter PowerSTDBY Power Standby Power Average Power Dissipation Condition Blocks in standby with SPI upload lux = 0, clock = 315 MHz, 500 fps Typ 400 1350 Units mW mW http://onsemi.com 5 5 Page NOIL2SM1300A Table 9. INTERNAL REGISTERS Block Register Name Address [6..0] AFE afepwd2 12 Bias block bandgap 13 Image Core imcmodes 14 Fix7 Fix8 imcbias1 imcbias2 imcbias3 Imcbias4 Data Block Fix9 Fix10 dataconfig1 15 16 17 18 19 20 21 22 23 dataconfig2 Fix11 dacvrefadc Fix12 Fix13 Fix14 datachannel0_1 24 25 26 27 28 29 30 Field [3:0] [0] [1] [2] [5:3] [0] [1] [2] [3] [4] [5] [7:0] [7:0] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [7:0] [7:0] [1:0] [2] [3] [4] [5] [7:6] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [0] [1] [2] [3] [5:4] Reset Value 0x00 ‘0’ ‘1’ ‘0’ ‘000’ 0 ‘1’ ‘1’ 0 ‘1’ ‘0’ 0x00 0x00 ‘1000’ ‘1000’ ‘1000’ ‘1000’ ‘1000’ ‘1000’ ‘1000’ ‘1000’ 0x20 0xC0 0x00 1 0 0 0 0x03 0x2A 0 0x84 0x80 0 0 0 0 0x00 Description Power down adc_channel_2x 11 to 8 Power down bandgap and currents External resistor External voltage reference Bandgap trimming Power down Enable vrefcol regulator Enable precharge regulator Disable internal bias for vprech Disable column load clkmain invert Reserved, fixed value Reserved, fixed value Bias colfpn DAC buffer Bias precharge regulator Bias pixel precharge level Bias column ota Bias column unip fast Bias column unip slow Bias column load Bias column precharge Reserved, fixed value Reserved, fixed value Reserved, fixed value ‘1’: Enables user upload of dacvrefadc register value ‘0’: Keeps default value Enable PRBS generation Reserved, fixed value Reserved, fixed value Training pattern inserted to sync LVDS receivers Training pattern inserted to sync LVDS receivers Reserved, fixed value Input to DAC to set the offset at the input of the ADC Reserved, fixed value Reserved, fixed value Reserved, fixed value Bypass the data block Enables the FPN correction Overwrite incoming ADC data by the data in the testpat register Reserved, fixed value Pattern inserted to generate a test image http://onsemi.com 11 11 Page

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