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PDF LC717A00AJ Data sheet ( Hoja de datos )

Número de pieza LC717A00AJ
Descripción Capacitance-Digital-Converter LSI
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No Preview Available ! LC717A00AJ Hoja de datos, Descripción, Manual

Ordering number : ENA2089A
LC717A00AJ
CMOS LSI
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
http://onsemi.com
Overview
The LC717A00AJ is a high-performance, low-cost capacitance-digital-converter LSI for electrostatic capacitive touch
sensor, especially focused on usability. It has 8 channels capacitance-sensor input. The built-in logic circuit can detect
the state (ON/OFF) of each input and output the result. This makes it ideal for various switch applications.
The calibration function is automatically performed by the built-in logic circuit during power activation or whenever
there are environmental changes. In addition, since initial settings of parameters, such as gain, are configured,
LC717A00AJ can operate as stand-alone when the recommended switch pattern is applied.
Also, since LC717A00AJ has a serial interface compatible with I2C and SPI bus, parameters can be adjusted using
external devices whenever necessary. Moreover, outputs of the 8-input capacitance data can be detected and measured
as 8-bit data.
Features
Detection system: Differential capacitance detection (Mutual capacitance type)
Input capacitance resolution: Can detect capacitance changes in the femto Farad order
Measurement interval (8 differential inputs): 18ms (Typ) (at initial configuration),
3ms (Typ) (at minimum interval configuration)
External components for measurement: Not required
Current consumption: 320μA (Typ) (VDD = 2.8V), 740μA (Typ) (VDD = 5.5V)
Supply voltage: 2.6V to 5.5V
Detection operations: Switch
Packages: SSOP30
Interface: I2C * compatible bus or SPI selectable.
* I2C Bus is a trademark of Philips Corporation.
Semiconductor Components Industries, LLC, 2013
August, 2013
Ver1.0.1
D1912HKPC 20121129-S00003/71112HK No.A2089-1/11

1 page




LC717A00AJ pdf
LC717A00AJ
Power-on Reset (POR)
When power is turned on, power-on reset is enabled inside the LSI and its state is released after a certain power-on reset
time, tPOR. Power-on reset operation condition: Power supply rise rate tVDD must be at least 1V/ms.
Since INTOUT pin changes from “High” to “Low” at the same time as the released of power-on reset state, it is
possible to verify the tPOR externally.
During power-on reset state, Cin, Cref and Pout are unknown.
VDD
tVDD
tPOR
POR
(LSI internal signal)
RESET
RELEASE
VPOROP
tPOROP
tPOR
UNKNOWN RESET
RELEASE
INTOUT
VALID UNKNOWN
Cin,
Cref,
Pout
UNKNOWN
VALID
UNKNOWN
I2C Compatible Bus Data Timing
fig.1
SDA
10%
90%
10%
SCL
tLOW
tHD;DTA tSU;DTA
90% 90%
90%
10% 10%
10%
tHIGH
10%
tHD;STA
tr tf
START
condition
tSU;STA
90%
90%
10%
tHD;STA
90%
repeated START
condition
fig.2
90%
10%
tSU;STO
tBUF
90%
10%
90%
STOP
condition
START
condition
I2C Compatible Bus Communication Formats
Write format (data can be written into sequentially incremented addresses)
START
Slave Address
Write=L ACK
Slave
Register Address (N)
ACK Data written to Register Address (N) ACK Data written to Register Address (N+1) ACK STOP
Slave
fig.3
Slave
Slave
Read format (data can be read from sequentially incremented addresses)
START
Slave Address
RESTART
Slave Address
Write=L ACK
Slave
Register Address (N)
ACK
Slave
Read=H ACK Data read from Register Address (N) ACK Data read from Register Address (N+1) ACK Data read from Register Address (N+2) NACK STOP
Slave
Master
fig.4
Master
Master
No.A2089-5/11

5 Page





LC717A00AJ arduino
LC717A00AJ
nCS
Interface selection / Chip-select-inverting input (SPI)
Selection of I2C compatible bus mode or SPI mode is through this terminal. After initialization, the LSI is
automatically in I2C compatible bus mode. To continually use I2C compatible bus mode, fix nCS pin to “High”. To
switch to SPI mode after LSI initialization, change the nCS input “High” “Low”. The nCS pin is used as the chip-
select-inverting input pin of SPI, and SPI mode is kept until LSI is again initialized.
If interface is not to be used, fix the pin to “High”.
nRST
It is the external-reset-signal-inverting-input pin. When nRST pin is “Low”, LSI is in the reset state.
Each pin (Cin0 to 7, Cref, Pout,0 to 7, ERROR) is “Hi-Z” during reset state.
SDA/SI
Data input and output (I2C) / Data input (SPI)
It is the data input and output pin of the I2C compatible bus or the data input pin of the SPI depending on the mode of
operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
SA/SO
Slave address selection (I2C) / Data output (SPI)
It is the slave address selection pin of the I2C compatible bus or the data output pin of the SPI depending on the mode
of operation.
If interface is not to be used, fix the pin to “High”. However, even if interface is not to be used, providing a
communication terminal on board is still recommended.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the
application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for
any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the
part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PS No.A2089-11/11

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